Abstract: A system is provided for an SMMU context save process in which only the configuration registers whose contents are changed following an SMMU initialization are saved to a system memory. Similarly, the system performs an SMMU context restore by only writing to the configuration registers whose context had changed prior to the SMMU context save process.

Abstract: Systems and methods are provided for enhancing the endurance of a Universal Flash Storage (UFS) device by providing a UFS pinned region relocation mechanism that relocates the UFS pinned region of the write booster buffer to a portion of the write booster buffer that was previously part of a non-pinned region of the write booster buffer based on an indication of the health of the UFS pinned region.

Abstract: Methods and apparatuses are provided that can establish data links with greater bandwidths within die-to-die interconnect architectures. In one example, a system-on-a-chip (SoC) includes an error status register, a plurality of data ports for a data link, and a processor electrically coupled to the error status register and to the plurality of data ports. The processor can receive error data from the error status register and, based on the error data, can determine a portion of the plurality of data ports that are error free. Further, the processor can determine a bandwidth for the data link based on the portion of the plurality of data ports that are error free. Further, the processor can initiate a link negotiation process to establish the link with another device based on the link width value and the portion of the plurality of data ports that are error free.

Abstract: Methods and apparatuses are provided that can establish data links with greater bandwidths within die-to-die interconnect architectures. In one example, a system-on-a-chip (SoC) includes an error status register, a plurality of data ports for a data link, and a processor electrically coupled to the error status register and to the plurality of data ports. The processor can receive error data from the error status register and, based on the error data, can determine a portion of the plurality of data ports that are error free. Further, the processor can determine a bandwidth for the data link based on the portion of the plurality of data ports that are error free. Further, the processor can initiate a link negotiation process to establish the link with another device based on the link width value and the portion of the plurality of data ports that are error free.

Abstract: Aspects of entry into self-refresh mode by a dynamic random-access memory (DRAM) may be managed using one or more polled registers. Indications of DRAM write activity by the DRAM or a DRAM client may be stored in the registers. The registers may be polled after entry into DRAM self-refresh mode is initiated. The DRAM's entry into self-refresh mode may not be allowed until the registers indicate absence of DRAM write activity.

Abstract: Methods and apparatuses directed to improving performance and data integrity within die architectures. In some examples, a die package includes a memory device, and a processor coupled to the memory device. The memory device may serve as a cache for another memory device. The processor receives a signal indicating that a number of errors have been detected. In response to the signal, the processor reads an error count corresponding to each of multiple memory rows of the memory device. Further, the processor determines a first memory row of the memory rows based on the error counts. The processor also determines a second memory row of the memory rows based on access data characterizing memory accesses of the plurality of rows. The processor further writes data stored at the first memory row to the second memory row of the memory device, and disables the first memory row.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support exception event handling and reporting. In a first aspect, a method of exception event handling in a flash memory system includes a host memory controller receiving a response from the memory system, the response comprising user data, an indication that an exception event was encountered by the memory system, and information regarding the exception event encountered by the memory system; and transmitting an acknowledgement of receiving the indication that the exception event was encountered by the memory system. Other aspects and features are also claimed and described.

Abstract: Methods and apparatuses directed to improving performance and data integrity within die architectures. In some examples, a die package includes a memory device, and a processor coupled to the memory device. The memory device may serve as a cache for another memory device. The processor receives a signal indicating that a number of errors have been detected. In response to the signal, the processor reads an error count corresponding to each of multiple memory rows of the memory device. Further, the processor determines a first memory row of the memory rows based on the error counts. The processor also determines a second memory row of the memory rows based on access data characterizing memory accesses of the plurality of rows. The processor further writes data stored at the first memory row to the second memory row of the memory device, and disables the first memory row.

Abstract: Methods that may be performed by a universal flash storage (UFS) system of a computing device for optimizing usage of a shared write booster buffer to extend lifetime.

Abstract: A multi-lane data communication link, such as a PCIe link, may be configured as virtual links. Each virtual link may correspond to a unique subset of the lanes. Data packets provided by multiple virtual machines and associated virtual functions may be buffered in transmit queues. Each transmit queue may correspond to a unique one of the virtual links. The data may be provided from each of the transmit queues to data transmitting circuitry coupled to active lanes.