Patents by Inventor Radhakrishnan Sithanandam

Radhakrishnan Sithanandam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12266927
    Abstract: Electrostatic discharge (ESD) protection is provided in circuits which use of a tunneling field effect transistor (TFET) or an impact ionization MOSFET (IMOS). These circuits are supported in silicon on insulator (SOI) and bulk substrate configurations to function as protection diodes, supply clamps, failsafe circuits and cutter cells. Implementations with parasitic bipolar devices provide additional parallel discharge paths.
    Type: Grant
    Filed: June 8, 2023
    Date of Patent: April 1, 2025
    Assignee: STMicroelectronics International N.V.
    Inventor: Radhakrishnan Sithanandam
  • Publication number: 20230318287
    Abstract: Electrostatic discharge (ESD) protection is provided in circuits which use of a tunneling field effect transistor (TFET) or an impact ionization MOSFET (IMOS). These circuits are supported in silicon on insulator (SOI) and bulk substrate configurations to function as protection diodes, supply clamps, failsafe circuits and cutter cells. Implementations with parasitic bipolar devices provide additional parallel discharge paths.
    Type: Application
    Filed: June 8, 2023
    Publication date: October 5, 2023
    Applicant: STMicroelectronics International N.V.
    Inventor: Radhakrishnan SITHANANDAM
  • Patent number: 11710961
    Abstract: Electrostatic discharge (ESD) protection is provided in circuits which use of a tunneling field effect transistor (TFET) or an impact ionization MOSFET (IMOS). These circuits are supported in silicon on insulator (SOI) and bulk substrate configurations to function as protection diodes, supply clamps, failsafe circuits and cutter cells. Implementations with parasitic bipolar devices provide additional parallel discharge paths.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: July 25, 2023
    Assignee: STMicroelectronics International N.V.
    Inventor: Radhakrishnan Sithanandam
  • Patent number: 11658479
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated MOSFET device. Triggering of the MOSFET device is made at both the gate terminal and the substrate (back gate) terminal. Additionally, the MOSFET device can be formed of cascoded MOSFETs.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: May 23, 2023
    Assignees: STMicroelectronics International N.V., STMicroelectronics SA
    Inventors: Radhakrishnan Sithanandam, Divya Agarwal, Ghislain Troussier, Jean Jimenez, Malathi Kar
  • Patent number: 11081881
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit including a trigger actuated MOSFET device. Triggering of the MOSFET device is made in response to detection of either a positive ESD event or a negative ESD event.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: August 3, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Divya Agarwal, Radhakrishnan Sithanandam
  • Publication number: 20210226445
    Abstract: Electrostatic discharge (ESD) protection is provided in circuits which use of a tunneling field effect transistor (TFET) or an impact ionization MOSFET (IMOS). These circuits are supported in silicon on insulator (SOI) and bulk substrate configurations to function as protection diodes, supply clamps, failsafe circuits and cutter cells. Implementations with parasitic bipolar devices provide additional parallel discharge paths.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 22, 2021
    Applicant: STMicroelectronics International N.V.
    Inventor: Radhakrishnan SITHANANDAM
  • Patent number: 11063429
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated MOSFET device. Triggering of the MOSFET device is made at both the gate terminal and the substrate (back gate) terminal. Additionally, the MOSFET device can be formed of cascoded MOSFETs.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: July 13, 2021
    Assignees: STMicroelectronics International N.V., STMicroelectronics SA
    Inventors: Radhakrishnan Sithanandam, Divya Agarwal, Ghislain Troussier, Jean Jimenez, Malathi Kar
  • Patent number: 10998721
    Abstract: Electrostatic discharge (ESD) protection is provided in circuits which use of a tunneling field effect transistor (TFET) or an impact ionization MOSFET (IMOS). These circuits are supported in silicon on insulator (SOI) and bulk substrate configurations to function as protection diodes, supply clamps, failsafe circuits and cutter cells. Implementations with parasitic bipolar devices provide additional parallel discharge paths.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: May 4, 2021
    Assignee: STMicroelectronics International N.V.
    Inventor: Radhakrishnan Sithanandam
  • Patent number: 10944257
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated SCR device. The SCR device may include an embedded field effect transistor (FET) having an insulated gate that receives a trigger signal from an ESD detection circuit. The SCR device may alternatively include a variable substrate resistor having an insulated gate that receives a trigger signal from an ESD detection circuit.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: March 9, 2021
    Assignees: STMicroelectronics International N.V., STMicroelectronics SA
    Inventors: Radhakrishnan Sithanandam, Divya Agarwal, Jean Jimenez, Malathi Kar
  • Publication number: 20200412124
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated MOSFET device. Triggering of the MOSFET device is made at both the gate terminal and the substrate (back gate) terminal. Additionally, the MOSFET device can be formed of cascoded MOSFETs.
    Type: Application
    Filed: September 9, 2020
    Publication date: December 31, 2020
    Applicants: STMicroelectronics International N.V., STMicroelectronics SA
    Inventors: Radhakrishnan SITHANANDAM, Divya AGARWAL, Ghislain TROUSSIER, Jean JIMENEZ, Malathi KAR
  • Patent number: 10811873
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit formed by an ESD event actuated transistor device. A bias current is generated in response to operation of a voltage independent current generator circuit. The bias current is sourced to ensure that the transistor device is deactuated after the ESD event is dissipated.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: October 20, 2020
    Assignee: STMicroelectronics International N.V.
    Inventors: Vicky Batra, Radhakrishnan Sithanandam
  • Publication number: 20190319453
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated MOSFET device. Triggering of the MOSFET device is made at both the gate terminal and the substrate (back gate) terminal. Additionally, the MOSFET device can be formed of cascoded MOSFETs.
    Type: Application
    Filed: April 12, 2018
    Publication date: October 17, 2019
    Applicants: STMicroelectronics International N.V., STMicroelectronics SA
    Inventors: Radhakrishnan SITHANANDAM, Divya AGARWAL, Ghislain TROUSSIER, Jean JIMENEZ, Malathi KAR
  • Publication number: 20190319454
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated SCR device. The SCR device may include an embedded field effect transistor (FET) having an insulated gate that receives a trigger signal from an ESD detection circuit. The SCR device may alternatively include a variable substrate resistor having an insulated gate that receives a trigger signal from an ESD detection circuit.
    Type: Application
    Filed: April 13, 2018
    Publication date: October 17, 2019
    Applicants: STMicroelectronics International N.V., STMicroelectronics SA
    Inventors: Radhakrishnan SITHANANDAM, Divya AGARWAL, Jean JIMENEZ, Malathi KAR
  • Publication number: 20190190256
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit including a trigger actuated MOSFET device. Triggering of the MOSFET device is made in response to detection of either a positive ESD event or a negative ESD event.
    Type: Application
    Filed: December 20, 2017
    Publication date: June 20, 2019
    Applicant: STMicroelectronics International N.V.
    Inventors: Divya Agarwal, Radhakrishnan Sithanandam
  • Publication number: 20190165571
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit formed by an ESD event actuated transistor device. A bias current is generated in response to operation of a voltage independent current generator circuit. The bias current is sourced to ensure that the transistor device is deactuated after the ESD event is dissipated.
    Type: Application
    Filed: November 28, 2017
    Publication date: May 30, 2019
    Applicant: STMicroelectronics International N.V.
    Inventors: Vicky Batra, Radhakrishnan Sithanandam
  • Publication number: 20180287378
    Abstract: Electrostatic discharge (ESD) protection is provided in circuits which use of a tunneling field effect transistor (TFET) or an impact ionization MOSFET (IMOS). These circuits are supported in silicon on insulator (SOI) and bulk substrate configurations to function as protection diodes, supply clamps, failsafe circuits and cutter cells. Implementations with parasitic bipolar devices provide additional parallel discharge paths.
    Type: Application
    Filed: March 1, 2018
    Publication date: October 4, 2018
    Applicant: STMicroelectronics International N.V.
    Inventor: Radhakrishnan Sithanandam