Patents by Inventor Radhika Srinivasan
Radhika Srinivasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6797582Abstract: A 3D microelectronic structure is provided which includes a substrate having at least one opening present therein, the at least one opening having sidewalls which extend to a common bottom wall; and a thermal nitride layer present on at least an upper portion of each sidewall of openings. A method for fabricating the above-mentioned 3D microelectronic structure is also provided. Specifically, the method includes a step of selectively forming a thermal nitride layer on at least an upper portion of each sidewall of an opening formed in a substrate.Type: GrantFiled: April 30, 2003Date of Patent: September 28, 2004Assignee: International Business Machines CorporationInventors: Oleg Gluschenkov, Michael P. Chudzik, Rajarao Jammy, Christopher C. Parks, Kenneth T. Settlemyer, Jr., Radhika Srinivasan, Kathryn H. Varian
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Publication number: 20030203587Abstract: A 3D microelectronic structure is provided which includes a substrate having at least one opening present therein, the at least one opening having sidewalls which extend to a common bottom wall; and a thermal nitride layer present on at least an upper portion of each sidewall of openings. A method for fabricating the above-mentioned 3D microelectronic structure is also provided. Specifically, the method includes a step of selectively forming a thermal nitride layer on at least an upper portion of each sidewall of an opening formed in a substrate.Type: ApplicationFiled: April 30, 2003Publication date: October 30, 2003Inventors: Oleg Gluschenkov, Michael P. Chudzik, Rajarao Jammy, Christopher C. Parks, Kenneth T. Settlemyer, Radhika Srinivasan, Kathryn H. Varian
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Publication number: 20030107111Abstract: A 3D microelectronic structure is provided which includes a substrate having at least one opening present therein, the at least one opening having sidewalls which extend to a common bottom wall; and a thermal nitride layer present on at least an upper portion of each sidewall of openings. A method for fabricating the above-mentioned 3D microelectronic structure is also provided. Specifically, the method includes a step of selectively forming a thermal nitride layer on at least an upper portion of each sidewall of an opening formed in a substrate.Type: ApplicationFiled: December 10, 2001Publication date: June 12, 2003Applicant: International Business Machines CorporationInventors: Oleg Gluschenkov, Michael P. Chudzik, Rajarao Jammy, Christopher C. Parks, Kenneth T. Settlemyer, Radhika Srinivasan, Kathryn H. Varian
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Patent number: 6348394Abstract: A semiconductor device and method of manufacturing thereof are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. A nitride liner is formed in the trench. Charge is trapped in the nitride liner. In a preferred embodiment, the trench is filled with an oxide by an HDP process to increase the amount of charge trapped in the nitride liner. Preferably, the oxide fill is formed directly on the nitride liner.Type: GrantFiled: May 18, 2000Date of Patent: February 19, 2002Assignee: International Business Machines CorporationInventors: Jack A. Mandelman, Rama Divakaruni, Herbert Ho, Giuseppe La Rosa, Yujun Li, Jochen Beintner, Radhika Srinivasan
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Patent number: 6333531Abstract: A process for forming a small grain structure in a material within a semiconductor device near the interface of an adjacent dissimilar material, to result in a highly diffusive grain structure. The highly diffusive grain structure formed within one material enhances diffusion of a dopant impurity, and provides for improved dopant control in an adjacent dissimilar material.Type: GrantFiled: January 29, 1999Date of Patent: December 25, 2001Assignee: International Business Machines CorporationInventors: Yun-Yu Wang, Johnathan E. Faltermeier, Philip L. Flaitz, Jeffery L. Hurd, Rajarao Jammy, Radhika Srinivasan, Francis G. Trudeau, Dinah S. Weiss
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Patent number: 6190955Abstract: Improved trench forming methods for semiconductor substrates using BSG avoid the problems associated with conventional TEOS hard mask techniques. The methods comprise: (a) providing a semiconductor substrate, (b) applying a conformal layer of borosilicate glass (BSG) on the substrate; (c) forming a patterned photoresist layer over the BSG layer whereby a portion of a layer underlying the photoresist layer is exposed, (d) anisotropically etching through the exposed portion of the underlying layer, through any other layers lying between the photoresist layer and the semiconductor substrate, and into the semiconductor substrate, thereby forming a trench in the semiconductor substrate. Preferably, one or more dielectric layers are present on the substrate surface prior to application of the BSG layer. One or more chemical barrier and/or organic antireflective coating layers may be applied over the BSG layer between the BSG layer and the photoresist layer.Type: GrantFiled: January 27, 1998Date of Patent: February 20, 2001Assignees: International Business Machines Corporation, Infineon Technologies North America Corp., Kabushiki Kaisha ToshibaInventors: Matthias Ilg, Richard L. Kleinhenz, Soichi Nadahara, Ronald W. Nunes, Klaus Penner, Klaus Roithner, Radhika Srinivasan, Shigeki Sugimoto
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Patent number: 6153474Abstract: The present invention includes a method and system to increase the deep trench sidewall surface area in a storage node on a DRAM chip. By tilting the trenches the capacitance is increased without taking up more space on the semiconductor chip.Type: GrantFiled: July 1, 1998Date of Patent: November 28, 2000Assignee: International Business Machines CorporationInventors: Herbert Lei Ho, Radhika Srinivasan, Scott D. Halle, Erwin Hammerl, David M. Dobuzinsky, Jack Allan Mandelman, Mark Anthony Jaso
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Patent number: 6140208Abstract: A reduction in parasitic leakages of shallow trench isolation vias is disclosed wherein the distance between the silicon nitride liner and the active silicon sidewalls is increased by depositing an insulating oxide layer prior to deposition of the silicon nitride liner. Preferably, the insulating oxide layer comprises tetraethylorthosilicate. The method comprises of etching one or more shallow trench isolations into a semiconductor wafer; depositing an insulating oxide layer into the trench; growing a thermal oxide in the trench; and depositing a silicon nitride liner in the trench. The thermal oxide may be grown prior to or after deposition of the insulating oxide layer.Type: GrantFiled: February 5, 1999Date of Patent: October 31, 2000Assignees: International Business Machines Corporation, Infineon Technologies North America Corp.Inventors: Farid Agahi, Gary Bronner, Bertrand Flietner, Erwin Hammerl, Herbert Ho, Radhika Srinivasan
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Patent number: 6130145Abstract: A reduced metal-rich interface between a poly and metal silicide layer is achieved by insitu doping the metal silicide layer.Type: GrantFiled: January 21, 1998Date of Patent: October 10, 2000Assignees: Siemens Aktiengesellschaft, International Business Machines CorporationInventors: Matthias Ilg, Johnathan Faltermeier, Radhika Srinivasan
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Patent number: 6074903Abstract: A method for forming a electrically isolated semiconductor devices in a silicon body. A trench is formed in a selected region of the body. A barrier material is deposited over sidewalls of the trench. Portions of the barrier material are removed from a first sidewall portion of the trench to expose such first sidewall portion of the trench while leaving portions of such barrier material on a second sidewall portion of the trench to form a barrier layer thereon. A dielectric material is deposited in the trench, a portion of dielectric material being deposited on the exposed first sidewall portion of the trench and another portion of such deposited dielectric material being deposited on the barrier material. The dielectric material is annealed in an oxidizing environment to densify such deposited dielectric material, the barrier layer inhibiting oxidation of the said second sidewall portion of the trench.Type: GrantFiled: June 16, 1998Date of Patent: June 13, 2000Assignees: Siemens Aktiengesellschaft, International Business Machines Corporation, Kabushiki Kaisha ToshibaInventors: Rajesh Rengarajan, Hirofumi Inoue, Radhika Srinivasan, Jochen Beintner
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Patent number: 5923971Abstract: Strap resistance, surface strap shorts and wordline capacitance can be reduced by providing a selectively grown silicon strap which tapers away from spacer nitride and has less contact with spacer nitride. In addition the strap is optionally doped with an arsenic implant which reduces resistance.Type: GrantFiled: October 22, 1996Date of Patent: July 13, 1999Assignee: International Business Machines CorporationInventors: Herbert L. Ho, Andre R. LeBlanc, Jack A. Mandelman, Radhika Srinivasan
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Patent number: 5893735Abstract: Method for forming three-dimensional device structures comprising a second device having sub-groundrule features formed over a first device is disclosed. A layer having a single crystalline top surface is formed above the first device to provide the base for forming the active area of the second device. the sub-groundrule feature is formed using mandrel and spacers.Type: GrantFiled: November 1, 1996Date of Patent: April 13, 1999Assignees: Siemens Aktiengesellschaft, International Business Machines CorporationInventors: Reinhard J. Stengl, Erwin Hammerl, Jack A. Mandelman, Herbert L. Ho, Radhika Srinivasan, Alvin P. Short, Bernhard Poschenrieder
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Patent number: 5844266Abstract: In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.Type: GrantFiled: June 20, 1997Date of Patent: December 1, 1998Assignee: Siemens AktiengesellschaftInventors: Reinhard Stengl, Erwin Hammerl, Herbert L. Ho, Jack A. Mandelman, Radhika Srinivasan, Alvin P. Short
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Patent number: 5827765Abstract: A method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell. The electrical connection is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.Type: GrantFiled: February 22, 1996Date of Patent: October 27, 1998Assignees: Siemens Aktiengesellschaft, International Business Machines CorporationInventors: Reinhard Stengl, Erwin Hammerl, Herbert L. Ho, Jack A. Mandelman, Radhika Srinivasan, Alvin P. Short
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Patent number: 5792685Abstract: Method for forming three-dimensional device structures comprising a second device formed over a first device is disclosed. A layer having a single crystalline top surface is formed above the first device to provide the base for forming the active area of the second device.Type: GrantFiled: June 21, 1996Date of Patent: August 11, 1998Assignees: Siemens Aktiengesellschaft, International Business Machines CorporationInventors: Erwin Hammerl, Jack A. Mandelman, Bernhard Poschenrieder, Alvin P. Short, Radhika Srinivasan, Reinhard J. Stengl, Herbert L. Ho
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Patent number: 5656535Abstract: A simplified method of fabricating a storage node for a deep trench-based DRAM on a semiconductor substrate. The method involves the etching a trench in a surface of the substrate and then forming a layer of dielectric material on a sidewall of the trench the top portion of which is subsequently removed from the sidewall. Next, a layer of oxide is grown on the exposed portion of the sidewall. A portion of this layer of oxide is then removed from the sidewall in order to orient the layer of oxide a predetermined distance from the surface of the substrate. Finally, the trench is filled with a semiconductive material.Type: GrantFiled: March 4, 1996Date of Patent: August 12, 1997Assignees: Siemens Aktiengesellschaft, International Business Machines CorporationInventors: Herbert Ho, Radhika Srinivasan, Scott D. Halle, Erwin Hammerl, David M. Dobuzinsky, Jack A. Mandelman, Mark Anthony Jaso