Patents by Inventor Radoslav Ratchkov
Radoslav Ratchkov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6835972Abstract: A multiple layer power mesh design includes an L-shaped structure and a bow tie-shaped structure. The L-shaped structure provides a plurality of L-shaped power rails in each of four quadrants of the layer. The bow tie-shaped structure includes plurality of vertical power rails in each of a left and right triangularly-shaped portion of the layer. The vertical power rails of the bow tie-shaped structure provide and interface between the upper and lower quadrants of the L-shaped layer. The bow tie-shaped structure provides additional available space which can, for example, be used for routing signal traces. A T-shaped structure is also provided for use with the bow tie-shaped layer. The T-shaped layer provides for improved distances between the VDD and the VSS power rails.Type: GrantFiled: May 9, 2003Date of Patent: December 28, 2004Assignee: LSI Logic CorporationInventors: Radoslav Ratchkov, Thomas Antisseril, Hiroshi Ishikawa, Prasad Subbarao, Bo Shen, Ruben Molina
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Patent number: 6781228Abstract: A multiple layer mesh design which includes a layer which provides a vertical mesh and an adjacent layer which provides a horizontal mesh which includes an open area or hole. The layer which provides the horizontal mesh (with hole) may either be above or below the vertical mesh layer, depending on the design. The vertical mesh may be full or may surround an open area or hole where the design includes both a horizontal donut mesh and a vertical donut mesh.Type: GrantFiled: January 10, 2003Date of Patent: August 24, 2004Assignee: LSI Logic CorporationInventors: Hiroshi Ishikawa, Thomas Antisseril, Radoslav Ratchkov, Bo Shen, Prasad Subbarao, Maad Al-Dabagh, Anwar Ali, Benjamin Mbouombouo
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Publication number: 20040135263Abstract: A multiple layer mesh design which includes a layer which provides a vertical mesh and an adjacent layer which provides a horizontal mesh which includes an open area or hole. The layer which provides the horizontal mesh (with hole) may either be above or below the vertical mesh layer, depending on the design. The vertical mesh may be full or may surround an open area or hole where the design includes both a horizontal donut mesh and a vertical donut mesh.Type: ApplicationFiled: January 10, 2003Publication date: July 15, 2004Inventors: Hiroshi Ishikawa, Thomas Antisseril, Radoslav Ratchkov, Bo Shen, Prasad Subbarao, Maad Al-Dabagh, Anwar Ali, Benjamin Mbouombouo
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Publication number: 20040129955Abstract: A multiple layer power mesh design includes an L-shaped structure and a bow tie-shaped structure. The L-shaped structure provides a plurality of L-shaped power rails in each of four quadrants of the layer. The bow tie-shaped structure includes plurality of vertical power rails in each of a left and right triangularly-shaped portion of the layer. The vertical power rails of the bow tie-shaped structure provide and interface between the upper and lower quadrants of the L-shaped layer. The bow tie-shaped structure provides additional available space which can, for example, be used for routing signal traces. A T-shaped structure is also provided for use with the bow tie-shaped layer. The T-shaped layer provides for improved distances between the VDD and the VSS power rails.Type: ApplicationFiled: May 9, 2003Publication date: July 8, 2004Inventors: Radoslav Ratchkov, Thomas Antisseril, Hiroshi Ishikawa, Prasad Subbarao, Bo Shen, Ruben Molina
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Publication number: 20040124521Abstract: A rectangular termination ring for a power distribution mesh is placed on the upper two layers of an integrated circuit and may be placed over some I/O circuitry. The strapping connecting the bonding pads to the termination ring are placed on upper levels of the integrated circuit, minimizing the via requirements and freeing space for additional circuitry. Further, the termination ring may be adapted to work in conjunction with L-shaped, as well as other power distribution meshes.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventors: Maad Al-Dabagh, Thomas Antisseril, Bo Shen, Prasad Subbarao, Radoslav Ratchkov
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Patent number: 6747349Abstract: A rectangular termination ring for a power distribution mesh is placed on the upper two layers of an integrated circuit and may be placed over some I/O circuitry. The strapping connecting the bonding pads to the termination ring are placed on upper levels of the integrated circuit, minimizing the via requirements and freeing space for additional circuitry. Further, the termination ring may be adapted to work in conjunction with L-shaped, as well as other power distribution meshes.Type: GrantFiled: December 31, 2002Date of Patent: June 8, 2004Assignee: LSI Logic CorporationInventors: Maad Al-Dabagh, Thomas Antisseril, Bo Shen, Prasad Subbarao, Radoslav Ratchkov
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Patent number: 6744081Abstract: An integrated circuit with a power and ground distribution system having a first conductive layer, a second conductive layer, and an insulating layer disposed between the first layer and the second layer. A first ring is formed in the first layer, where the first ring forms a first loop around a peripheral portion of the integrated circuit. First straps are formed in the first layer, where the first straps have connections to the first ring. First horizontal members are formed in the first layer, where the first horizontal members have connections to the first ring. Second horizontal members are formed in the first layer, where the second horizontal members do not have connections to the first ring. A second ring is formed in the second layer, where the second ring forms a second loop around the peripheral portion of the integrated circuit. The second ring is interleaved with the first ring. Second straps are formed in the second layer, where the second straps have connections to the second ring.Type: GrantFiled: October 30, 2002Date of Patent: June 1, 2004Assignee: LSI Logic CorporationInventors: Radoslav Ratchkov, Maad Al-Dabagh
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Publication number: 20040085099Abstract: An integrated circuit with a power and ground distribution system having a first conductive layer, a second conductive layer, and an insulating layer disposed between the first layer and the second layer. A first ring is formed in the first layer, where the first ring forms a first loop around a peripheral portion of the integrated circuit. First straps are formed in the first layer, where the first straps have connections to the first ring. First horizontal members are formed in the first layer, where the first horizontal members have connections to the first ring. Second horizontal members are formed in the first layer, where the second horizontal members do not have connections to the first ring. A second ring is formed in the second layer, where the second ring forms a second loop around the peripheral portion of the integrated circuit. The second ring is interleaved with the first ring. Second straps are formed in the second layer, where the second straps have connections to the second ring.Type: ApplicationFiled: October 30, 2002Publication date: May 6, 2004Inventors: Radoslav Ratchkov, Maad Al-Dabagh
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Patent number: 6674176Abstract: A wire bond package for an integrated circuit die includes a first I/O core ring and a second I/O core ring formed in a first metal layer; a pad strap formed in a second metal layer overlapping the second I/O core ring; a via formed between the first metal layer and the second metal layer where the second I/O core ring and the pad strap overlap; a first core ring formed in a third metal layer overlapping the first I/O core ring; a via formed between the first metal layer and the third metal layer where the first I/O core ring and the first core ring overlap outside the power strap; a first power mesh formed in a fourth metal layer overlapping the first core ring; and a via formed between the third metal layer and the fourth metal layer where the first core ring and the first power mesh overlap.Type: GrantFiled: February 20, 2002Date of Patent: January 6, 2004Assignee: LSI Logic CorporationInventor: Radoslav Ratchkov
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Publication number: 20030155633Abstract: A wire bond package for an integrated circuit die includes a first I/O core ring and a second I/O core ring formed in a first metal layer; a pad strap formed in a second metal layer overlapping the second I/O core ring; a via formed between the first metal layer and the second metal layer where the second I/O core ring and the pad strap overlap; a first core ring formed in a third metal layer overlapping the first I/O core ring; a via formed between the first metal layer and the third metal layer where the first I/O core ring and the first core ring overlap outside the power strap; a first power mesh formed in a fourth metal layer overlapping the first core ring; and a via formed between the third metal layer and the fourth metal layer where the first core ring and the first power mesh overlap.Type: ApplicationFiled: February 20, 2002Publication date: August 21, 2003Inventor: Radoslav Ratchkov
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Patent number: 6545288Abstract: A software tool and method for routing paths in a routing space. A grid is effectively built “on the fly”, therefore reducing the number of grid points which must be plotted. The boundaries of the routing space are defined. Blocks are then defined in the routing space. After the blocks have been defined, grid points are plotted corresponding to the corners of the blocks. The source points and target points are plotted, and grid points are plotted corresponding to the source and target points. Then, the paths from the source points to the target points are plotted along grid points which have been defined in the routing space. This process of defining the grid points not only reduces the size of data needed to describe the available routing space, but preferably obviates the need to run design rule checks.Type: GrantFiled: March 8, 2001Date of Patent: April 8, 2003Assignee: LSI Logic CorporationInventors: Radoslav Ratchkov, Anand Sethuraman