Abstract: One embodiment of the present invention includes a column multiplexer for accessing data from a memory array comprising an output node having a logic state that is based on a logic state of a control node, and column elements, each comprising a first pair of series connected switches controlled by a column select signal and a bit line signal associated with data stored in a plurality of memory cells. The first pair of switches is configured to set the control node to a logic low state based on a logic state of the bit line signal. The column elements each also comprise a second pair of series connected switches controlled by the bit line signal and a complement of the column select signal. The second pair of switches is configured to set the control node to a logic high state based on the logic state of the bit line signal.

Abstract: One embodiment of the present invention includes a column multiplexer for accessing data from a memory array comprising an output node having a logic state that is based on a logic state of a control node, and column elements, each comprising a first pair of series connected switches controlled by a column select signal and a bit line signal associated with data stored in a plurality of memory cells. The first pair of switches is configured to set the control node to a logic low state based on a logic state of the bit line signal. The column elements each also comprise a second pair of series connected switches controlled by the bit line signal and a complement of the column select signal. The second pair of switches is configured to set the control node to a logic high state based on the logic state of the bit line signal.

Abstract: One embodiment of the present invention includes a column multiplexer for accessing data from a memory array comprising an output node having a logic state that is based on a logic state of a control node, and column elements, each comprising a first pair of series connected switches controlled by a column select signal and a bit line signal associated with data stored in a plurality of memory cells. The first pair of switches is configured to set the control node to a logic low state based on a logic state of the bit line signal. The column elements each also comprise a second pair of series connected switches controlled by the bit line signal and a complement of the column select signal. The second pair of switches is configured to set the control node to a logic high state based on the logic state of the bit line signal.

Abstract: One embodiment of the present invention relates to a read only memory (ROM) that includes a memory cell pair. The memory cell pair includes a first memory cell and a second memory cell that share a common drain that is associated with the memory cell pair. The memory cell also includes a bitline configured to provide data from the first and second memory cells, wherein the bitline is electrically isolated from the common drain. Other methods and systems are also disclosed.

Abstract: One embodiment of the present invention relates to a read only memory (ROM) that includes a memory cell pair. The memory cell pair includes a first memory cell and a second memory cell that share a common drain that is associated with the memory cell pair. The memory cell also includes a bitline configured to provide data from the first and second memory cells, wherein the bitline is electrically isolated from the common drain. Other methods and systems are also disclosed.

Abstract: One embodiment of the present invention includes a column multiplexer for accessing data from a memory array comprising an output node having a logic state that is based on a logic state of a control node, and column elements, each comprising a first pair of series connected switches controlled by a column select signal and a bit line signal associated with data stored in a plurality of memory cells. The first pair of switches is configured to set the control node to a logic low state based on a logic state of the bit line signal. The column elements each also comprise a second pair of series connected switches controlled by the bit line signal and a complement of the column select signal. The second pair of switches is configured to set the control node to a logic high state based on the logic state of the bit line signal.

Abstract: A content addressable memory (CAM) is provided that can perform wide word searches. At least one CAM memory core having a plurality of bit pattern entry rows is included in the CAM. In addition, search logic is included that, is capable searching particular rows during each cycle. The search logic is also capable of allowing match line results of unsearched rows to remain unchanged during a cycle. The CAM further includes a serial AND array in communication with the bit pattern entry rows, wherein the serial AND array is capable of computing a match result for wide word entries that span multiple bit pattern entry rows. In one aspect, a match line enable signal is provided to the serial AND array, which facilitates computation of the match result.

Abstract: An invention is provided for low power searching in a CAM using sample words to save power in the compare lines. The invention includes comparing a sample section of stored data to a corresponding sample section of search data on a plurality of rows in the CAM. If a sample section of the stored data on any row of the plurality of rows is equivalent to the corresponding sample section of the search data, a remaining section of search data is allowed to propagate to the local compare lines coupled to the remaining section of the stored data of each row. However, if the sample section of the stored data is different from the corresponding sample section of the search data, the local compare lines coupled to the remaining section of the stored data on each row are latched.

Abstract: An invention is disclosed for reducing power in a CAM using sample words. A sample section of stored data is compared to a corresponding sample section of search data. If the sample section of the stored data is different from the corresponding section of the search data, a non-match result is generated. However, if the sample section of the stored data is equivalent to the corresponding sample section of the search data, the remaining section of the stored data is compared to a corresponding remaining section of the search data. Thus, the remaining section of the stored data is not compared to the corresponding remaining section of the search data if the sample section of the stored data is different from the corresponding section of the search data.

Abstract: A content addressable memory (CAM) is provided. The CAM includes a search port for performing search operations at each clock cycle and a maintenance port for writing and reading data to address locations of the content addressable memory. An interlock signal is also provided and is communicated from the search port to the maintenance port to establish when writing and reading of data is to be performed to the content addressable memory so that the search operations continue uninterrupted at each clock cycle. Preferably, the interlock signal is communicated at an end of a search operation and at a beginning of a search pre-charge operation. The maintenance port is configured to set-up a writing operation at a beginning of a clock cycle and execute the write operation at the end of the search operation and the beginning of the search pre-charge operation. In another preferred example, search operations can be deselected at any time, yet any desired writing and reading operation can still be executed.

Abstract: Modifications to CAM cell designs are required as supply voltages utilized decrease. In one possible modified design, when a reference bit applied to the CAM cell matches a stored bit, p-channel pass transistors within the CAM cell can pass a full logical high to an n-channel chain transistor coupled within a NAND configuration with other CAM cells. This full logical high can result in increased transition speed, a decrease in degradation, and/or a decrease in power dissipation for the n-channel chain transistor. Further, compared to using n-channel pass transistors, the use of p-channel pass transistors to transfer the logical high voltage can increase the transition speed, decrease the degradation, and/or decrease the power dissipation for the pass transistors. Alternatively, the use of n-channel pass transistors and a p-channel chain transistor can gain similar advantages if the logic was opposite.

Abstract: A content addressable memory (CAM) is provided that can perform wide word searches. At least one CAM memory core having a plurality of bit pattern entry rows is included in the CAM. In addition, search logic is included that, is capable searching particular rows during each cycle. The search logic is also capable of allowing match line results of unsearched rows to remain unchanged during a cycle. The CAM further includes a serial AND array in communication with the bit pattern entry rows, wherein the serial AND array is capable of computing a match result for wide word entries that span multiple bit pattern entry rows. In one aspect, a match line enable signal is provided to the serial AND array, which facilitates computation of the match result.

Abstract: An invention is provided for low Low power searching in a CAM using uses sample words to save power in the compare lines. The invention A method includes comparing a sample section of stored data to a corresponding sample section of search data on a plurality of rows in the CAM. If a sample section of the stored data on any row of the plurality of rows is equivalent to the corresponding sample section of the search data, a remaining section of search data is allowed to propagate to the local compare lines coupled to the remaining section of the stored data of each row. However, if the sample section of the stored data is different from the corresponding sample section of the search data, the local compare lines coupled to the remaining section of the stored data on each row are latched.