Abstract: A decoder circuit formed on an integrated circuit substrate including at least one short channel depletion transistor having a low resistance path formed between the source and the drain regions. The low resistance path is provided by an implant into the channel region that forms a depletion channel wherein the channel region has a length less than a length of a channel region of transistors in the decoder circuit that handle input/output voltage levels for the decoder circuit.

Abstract: An integrated circuit ("IC") having three different oxide layer thicknesses and a process for manufacturing the IC using a single oxide growth step is provided. A first region is formed on a substrate surface with oxidation enhancing properties. A second region is formed on the substrate surface with a dose of nitrogen that retards oxidation. An oxide layer is grown from the first and the second regions and a third region of the substrate such that the first, second, and third regions yield a first oxide layer for the capacitor, a second oxide layer for the read transistor and a third oxide layer for the write transistor.

Abstract: An integrated circuit device and manufacturing process wherein a first region is formed in a substrate with a dopant that enhances oxide formation and a second region is formed in the substrate with a dose of nitrogen that retards oxide formation. An oxide layer is grown over the first and the second regions and over a third region of the substrate such that the first, second, and third regions yield differing thicknesses of the oxide layer.