Abstract: The present invention includes a family of level converting flip-flops that accepts data and clock inputs at a lower voltage level while producing data outputs at a higher voltage level. These flip-flops enable fine-grained dual supply voltage techniques such as low-swing clocking (distributing the clock signal at a lower voltage level) and clustered voltage scaling (CVS). The level conversion is accomplished in a very efficient manner by sharing the positive feedbacks inside a flip-flop for both storage and level conversion. Additionally, the presented flip-flops are contention-free and non-ratioed, thus having reduced timing and power overheads due to the level conversion function.

Abstract: A double edge triggered circuit includes a clock gater responsive to a clock signal and an enable signal to output a gated clock signal, a first double edge triggered flip-flop that launches a data signal in response to the gated clock signal, and a second double edge triggered flip-flop that captures the data signal in response to the clock signal, wherein the clock gater stops the gated clock signal at a first logic value when the enable signal is at a first logic state, and the clock gater switches the gated clock signal from the first logic value at a next clock edge when the enable signal is at a second logic state.

Abstract: In one embodiment of the invention, a method for designing an integrated circuit is disclosed. The method includes automatically partitioning clock sinks of an integrated circuit design into a plurality of partitions; automatically synthesizing a clock tree from a master clock generator into the plurality of partitions to minimize local clock skew within each of the plurality of partitions; and automatically synthesizing clock de-skew circuitry into each of the plurality of partitions to control clock skew between neighboring partitions.

Abstract: A method is provided to formally verify a property of a circuit design comprising: receiving a description of at least a portion of the circuit; receiving an indication of search accuracy criteria; receiving a description of a relationship between current and voltage (I-V relationship) for one or more of devices of the circuit; converting each I-V relationship to a conservative approximation of such I-V relationship; assigning voltage labels to one or more terminals of one or more identified devices that indicate voltage relationships among the one or more terminals consistent with KVL; defining a respective current relationship among one or more respective sets of currents of the one or more of the identified devices that is consistent with KCL; searching for one or more combinations of current and voltage values that are within at least one region of each conservative approximation and that are consistent with the voltage labels and that are consistent with each respective defined current relationship; conv

Abstract: In one embodiment of the invention, a method for designing an integrated circuit is disclosed. The method includes automatically partitioning clock sinks of an integrated circuit design into a plurality of partitions; automatically synthesizing a clock tree from a master clock generator into the plurality of partitions to minimize local clock skew within each of the plurality of partitions; and automatically synthesizing clock de-skew circuitry into each of the plurality of partitions to control clock skew between neighboring partitions.

Abstract: A double edge triggered circuit includes a clock gater responsive to a clock signal and an enable signal to output a gated clock signal, a first double edge triggered flip-flop that launches a data signal in response to the gated clock signal, and a second double edge triggered flip-flop that captures the data signal in response to the clock signal, wherein the clock gater stops the gated clock signal at a first logic value when the enable signal is at a first logic state, and the clock gater switches the gated clock signal from the first logic value at a next clock edge when the enable signal is at a second logic state.

Abstract: The present invention includes a family of level converting flip-flops that accepts data and clock inputs at a lower voltage level while producing data outputs at a higher voltage level. These flip-flops enable fine-grained dual supply voltage techniques such as low-swing clocking (distributing the clock signal at a lower voltage level) and clustered voltage scaling (CVS). The level conversion is accomplished in a very efficient manner by sharing the positive feedbacks inside a flip-flop for both storage and level conversion. Additionally, the presented flip-flops are contention-free and non-ratioed, thus having reduced timing and power overheads due to the level conversion function.

Abstract: Intrinsic variations and challenging leakage control in current bulk-Si MOSFETs force undesired tradeoffs to be made and limit the scaling of SRAM circuits. Circuits and mechanisms are taught herein which improve leakage and noise margin in SRAM cells, such as those comprising either six-transistor (6-T) SRAM cell designs, or four-transistor (4-T) SRAM cell designs. The inventive SRAM cells utilize a feedback means coupling a portion of the storage node to a back-gate of an access transistor. Preferably feedback is coupled in this manner to both access transistors. SRAM cells designed with this built-in feedback achieve significant improvements in cell static noise margin (SNM) without area penalty. Use of the feedback scheme also results in the creation of a practical 4-T FinFET-based SRAM cell that achieves sub-100 pA per-cell standby current and offers similar improvements in SNM as the 6-T cell with feedback.