Abstract: In some embodiments, a circuit may include an input configured to receive a signal and a radix-r input/output pruning fast Fourier transform (FFT) processing element coupled to the input. The radix-r input/output pruning FFT processing element may be configured to remove FFT operations on input values of zero within the signal and to determine a discrete Fourier Transform (DFT) output having fewer output values than a number of input values of the signal.

Abstract: In some embodiments, a circuit may include an input configured to receive a signal and a radix-23 fast Fourier transform (FFT) processing element coupled to the input. The radix-23 FFT processing element may be configured to control variation of twiddle factors during calculation of a complete FFT through a plurality of processing stages. The radix-23 FFT processing element may be configured to incorporate the twiddle factors and adder tree matrices of the calculation into a single stage.

Abstract: In some embodiments, a circuit may include an input configured to receive a signal and a radix-r fast Fourier transform (FFT) processing element coupled to the input. The radix-r FFT processing element may be configured to subdivide data of size N into r equal sub-domains of size N/r?1 to determine specific frequencies.

Abstract: In some embodiments, an apparatus may include a memory configured to store data at a plurality of addresses and a processor circuit including a plurality of processor cores. Each processor core may include multiple threads. The processor circuit may be configured to subdivide an input data stream into a plurality of three-dimensional matrices corresponding to a number of processor cores of the processor circuit. The processor circuit may be further configured to associate each matrix with a respective one of the plurality of processor cores and determine concurrently a three-dimensional FFT for each matrix of the plurality of three-dimensional matrices within the respective one of the plurality of processor cores to produce an FFT output.

Abstract: In some embodiments, an apparatus can include a memory configured to store data at a plurality of addresses and a generalized radix-r fast Fourier transform (FFT) processor configured to determine a plurality of FFTs for any positive integer Discrete Fourier Transform (DFT) by utilizing three counters to access the data and the coefficient multipliers at each stage of the FFT processor.