Abstract: An integrated circuit voltage regulator includes a transconductor first stage; and a negative impedance cancellation stage, where the negative impedance cancellation stage comprises cross-coupled transistors at outputs of said transconductor first stage, and resistors in the transconductor first stage and the negative impedance cancellation stage introduce zeros in a transfer function, compensating for parasitic poles. The resistors may compensate for parasitic capacitance inherent in transistors. Load transistors may be coupled to outputs of the transconductance first stage. The voltage regulator may be implemented in a Complementary Metal-Oxide-Semiconductor (CMOS) structure, which may be a system-on-chip integrated circuit. The voltage regulator may provide immunity to power supply noise. The negative impedance cancellation stage may include differential input transistors coupled to the cross-coupled transistors.

Abstract: An integrated circuit voltage regulator includes a transconductor first stage; and a negative impedance cancellation stage, where the negative impedance cancellation stage comprises cross-coupled transistors at outputs of said transconductor first stage, and resistors in the transconductor first stage and the negative impedance cancellation stage introduce zeros in a transfer function, compensating for parasitic poles. The resistors may compensate for parasitic capacitance inherent in transistors. Load transistors may be coupled to outputs of the transconductance first stage. The voltage regulator may be implemented in a Complementary Metal-Oxide-Semiconductor (CMOS) structure, which may be a system-on-chip integrated circuit. The voltage regulator may provide immunity to power supply noise. The negative impedance cancellation stage may include differential input transistors coupled to the cross-coupled transistors.

Abstract: An integrated circuit voltage regulator includes a transconductor first stage; and a negative impedance cancellation stage, where the negative impedance cancellation stage comprises cross-coupled transistors at outputs of said transconductor first stage, and resistors in the transconductor first stage and the negative impedance cancellation stage introduce zeros in a transfer function, compensating for parasitic poles. The resistors may compensate for parasitic capacitance inherent in transistors. Load transistors may be coupled to outputs of the transconductance first stage. The voltage regulator may be implemented in a Complementary Metal-Oxide-Semiconductor (CMOS) structure, which may be a system-on-chip integrated circuit. The voltage regulator may provide immunity to power supply noise. The negative impedance cancellation stage may include differential input transistors coupled to the cross-coupled transistors.

Abstract: An integrated circuit voltage regulator includes a transconductor first stage; and a negative impedance cancellation stage, where the negative impedance cancellation stage comprises cross-coupled transistors at outputs of said transconductor first stage, and resistors in the transconductor first stage and the negative impedance cancellation stage introduce zeros in a transfer function, compensating for parasitic poles. The resistors may compensate for parasitic capacitance inherent in transistors. Load transistors may be coupled to outputs of the transconductance first stage. The voltage regulator may be implemented in a Complementary Metal-Oxide-Semiconductor (CMOS) structure, which may be a system-on-chip integrated circuit. The voltage regulator may provide immunity to power supply noise. The negative impedance cancellation stage may include differential input transistors coupled to the cross-coupled transistors.

Abstract: An integrated circuit voltage regulator uses a simple CMOS structure to implement a High Unity Gain BandWidth voltage regulator providing for low voltage ripple at the output of the regulator up to high frequencies in the hundreds of MHz range. A transconductor first stage is followed by an impedance cancellation second stage allowing DC gain to be set completely independently of the bandwidth.

Abstract: Methods and systems for integrated circuit design using dynamic voltage scaling may comprise (a) designing an IC to meet a voltage dependent frequency specification, the IC design including feedback circuitry for controlling a power supply voltage to a fabricated instance of the IC design, (b) characterizing a fabrication process for corner lots for the IC design at a range of power supply voltage levels achievable by the feedback circuitry; (c) validating the IC design against the fabrication process if the frequency specification is achievable for essentially all instances of the IC design fabricated, wherein the feedback circuitry in each IC resulting from the IC design is operable to respectively adjust the power supply voltage of each IC resulting from the IC design by reducing the power supply voltage if the IC is from a fast corner lot and increasing power supply voltage if from a slow corner lot.

Abstract: Methods and systems for integrated circuit design using dynamic voltage scaling may comprise (a) designing an IC to meet a voltage dependent frequency specification, the IC design including feedback circuitry for controlling a power supply voltage to a fabricated instance of the IC design, (b) characterizing a fabrication process for corner lots for the IC design at a range of power supply voltage levels achievable by the feedback circuitry; (c) validating the IC design against the fabrication process if the frequency specification is achievable for essentially all instances of the IC design fabricated, wherein the feedback circuitry in each IC resulting from the IC design is operable to respectively adjust the power supply voltage of each IC resulting from the IC design by reducing the power supply voltage if the IC is from a fast corner lot and increasing power supply voltage if from a slow corner lot.

Abstract: A method and an apparatus from such method for designing an integrated circuit (IC) that mitigates the effects of process, voltage, and temperature dependent characteristics on the fabrication of advanced IC's but provides high die yields, lower power usage, and faster circuits. Conventional design process takes into account power supply voltage Vdd as a variable that must be considered in a skewed corner analysis. The disclosure teaches that the IC design process can be substantially simplified by essentially factoring out voltage based variations in corner lot analysis for IC designs that include dynamic voltage scaling circuitry, because each fabricated IC die of an IC design having dynamic voltage scaling can individually adjust the applied supply voltage Vdd within a range to offset local process-induced variations in the performance of that specific IC die.

Abstract: A method and an apparatus from such method for designing an integrated circuit (IC) that mitigates the effects of process, voltage, and temperature dependent characteristics on the fabrication of advanced IC's but provides high die yields, lower power usage, and faster circuits. Conventional design process takes into account power supply voltage Vdd as a variable that must be considered in a skewed corner analysis. The disclosure teaches that the IC design process can be substantially simplified by essentially factoring out voltage based variations in corner lot analysis for IC designs that include dynamic voltage scaling circuitry, because each fabricated IC die of an IC design having dynamic voltage scaling can individually adjust the applied supply voltage Vdd within a range to offset local process-induced variations in the performance of that specific IC die.

Abstract: An integrated circuit voltage regulator uses a simple CMOS structure to implement a High Unity Gain BandWidth voltage regulator providing for low voltage ripple at the output of the regulator up to high frequencies in the hundreds of MHz range. A transconductor first stage is followed by an impedance cancellation second stage allowing DC gain to be set completely independently of the bandwidth.

Abstract: Various systems and methods are provided for adaptive equalization. The adaptive equalization is performed on a data signal received from a channel in a receiver. The data signal is equalized using an equalizer in the receiver, thereby generating an equalized data signal. During equalization, an equalization setting of the equalizer is adapted based upon an overshoot of the equalized data signal at a data transition.

Abstract: An IC package includes ground paddle(s), power paddle(s), a lead frame, a die, and electrically conductive input/output circuit pads, ground circuit pads, and bond wires. The lead frame may include input/output (I/O) pads positioned near the perimeter of the lead frame and around the ground paddle(s) and power paddle(s). The die may be positioned on one of the ground paddles and may include die terminals. Each I/O circuit pad may be positioned on and connected with one of the I/O pads. The ground circuit pads may be positioned on said one ground paddle around the die between the die and the I/O circuit pads. Each ground circuit pad may be connected to said one ground paddle. Each bond wire may connect a die terminal to an I/O circuit pad and/or a ground circuit pad. A bond wire may connect a die terminal to a power paddle.

Abstract: A system and method for enhancing the dynamic range of a receiver without degrading the signal to noise ratio of an incoming signal is disclosed. In one embodiment, an enhanced dynamic range receiver for receiving an incoming signal and processing the incoming signal comprises a plurality of VGAs alternately connected in series with a plurality of equalizers to form a VGA-equalizer chain, the VGA-equalizer chain adapted to receive the incoming signal and operable to generate a first analog signal, a first PD adapted to receive the first analog signal and operable to adjust the equalizers' coefficient values, and a second PD adapted to receive a second analog signal from a selected node in the VGA-equalizer chain and operable to adjust the gain of the VGAs.

Abstract: An adaptive equalization method and system for automatically adjusting an equalizer to compensate a signal's frequency dependent loss is disclosed. The method comprises setting the equalizer's initial coefficient value, receiving an equalized signal, identifying a positive to zero transition of the equalized signal, generating a common mode voltage from the equalized signal, and determining the equalized signal's tail settling voltage. The method further comprises comparing the equalized signal's tail settling voltage to the common mode voltage, determining if the signal is over equalized or under equalized based on the comparison, and adjusting the equalizer's coefficient value based on whether the signal is under equalized or over equalized.

Abstract: A process, temperature and supply insensitive trapezoidal pulse generator includes a stable reference current source for generating a stable reference current. The trapezoidal pulse generator includes a current amplification circuit adapted to receive the stable reference current and operable responsive to the stable reference current to amplify the stable reference current to a mirrored current. The trapezoidal pulse generator includes an output circuit coupled to the current amplification circuit and adapted to receive the mirrored current and operable in a second frequency to generate a trapezoidal pulse.

Abstract: A system and method for enhancing the dynamic range of a receiver without degrading the signal to noise ratio of an incoming signal is disclosed. In one embodiment, an enhanced dynamic range receiver for receiving an incoming signal and processing the incoming signal comprises a plurality of VGAs alternately connected in series with a plurality of equalizers to form a VGA-equalizer chain, the VGA-equalizer chain adapted to receive the incoming signal and operable to generate a first analog signal, a first PD adapted to receive the first analog signal and operable to adjust the equalizers' coefficient values, and a second PD adapted to receive a second analog signal from a selected node in the VGA-equalizer chain and operable to adjust the gain of the VGAs.

Abstract: An adaptive equalization method and system for automatically adjusting an equalizer to compensate a signal's frequency dependent loss is disclosed. The method comprises setting the equalizer's initial coefficient value, receiving an equalized signal, identifying a positive to zero transition of the equalized signal, generating a common mode voltage from the equalized signal, and determining the equalized signal's tail settling voltage. The method further comprises comparing the equalized signal's tail settling voltage to the common mode voltage, determining if the signal is over equalized or under equalized based on the comparison, and adjusting the equalizer's coefficient value based on whether the signal is under equalized or over equalized.

Abstract: A process, temperature and supply insensitive trapezoidal pulse generator includes a stable reference current source for generating a stable reference current. The trapezoidal pulse generator includes a current amplification circuit adapted to receive the stable reference current and operable responsive to the stable reference current to amplify the stable reference current to a mirrored current. The trapezoidal pulse generator includes an output circuit coupled to the current amplification circuit and adapted to receive the mirrored current and operable in a second frequency to generate a trapezoidal pulse.

Abstract: An analog offset cancellation technique is based on the observation that the voltage developed across an inductor is proportional to the time derivative of the current passing through the inductor. An input voltage that may contain an undesired DC offset voltage is converted to a current that is representative of the input voltage. The resulting input current is passed through an inductor and the voltage generated across the inductor is used as the new input voltage. Because the voltage developed across the inductor is equal to the time derivative of the current passing through the inductor, the resulting voltage, the new input voltage, is independent of any DC components.

Abstract: Methods and apparatus to tune a transconductance stage include a current source and a six inverting amplifier stage. The current source establishes the biasing points of first and second inverting amplifiers, which in turn, provide a signal to a common mode feedback loop. By establishing the biasing points of the first and second inverting amplifiers, the transconductance of these inverting amplifiers may be controlled. Control of the transconductance permits control of the cut-off frequency of the transconductance stage. Furthermore, the ability to control the transconductance allows for control of the DC gain. In addition, establishing the biasing points of third and fourth inverting amplifiers by a second current source further controls the transconductance of these inverting amplifiers. Thus, further control of the transconductance permits further control of the cut-off frequency and DC gain of the transconductance stage. Therefore, tunability of the transconductance stage is provided.