Abstract: A System On Chip (SOC) has been provided which includes a crossbar switch between 64 functional I/Os internal to the chip, and 40 external connection pins. The crossbar switch permits a signal at any of the 64 functional I/Os to appear at any of the connector pins. The cross bar switch, permitting signals at the 40 connector pins to appear at any of the 64 specified functional I/Os. Because the switching is done with 4-way switches, the total number of hierarchical switch layers is reduced to 3. A parallel, opposite oriented, network of switches permits input signals delivered to the physical I/Os to be switched to any of the 64 functional I/Os. The small number of switch layers permit connections to be made with a minimum of delay across the switch. A method corresponding to the above-described crossbar switch system is also provided.

Abstract: A system and method has been provided to selectively deliver a plurality of trigger signals to a counter/timer embedded in a microprocessor. The method provides the step of selecting a signal, from either internal or external sources, to trigger the counter/timer. If an internal source is selected, the method provides the step of selecting either a synchronous or non-synchronous signal source to trigger the counter/timer. Regardless of the source chosen, the method includes the step of generating a signal output from the selected source, and the further step of delivering the trigger signal on a dedicated connection. The method of the present invention also includes the step of counting clock cycles in response to the arrival of the trigger signal to the counter/timer. An apparatus to selectively deliver a trigger signal to a counter/timer embedded in a microprocessor from a plurality of signal sources is also provided.

Abstract: A testing and diagnostic mechanism includes an external bus master allows access of virtually all internal registers on an integrated circuit, and allows the on-chip SRAM/DRAM controllers to access external memory.