Abstract: Provided are a method and electronic device for identifying a size of a measurement target object. The method includes imaging a reference object, which is a reference for identifying the size of the measurement target object, to acquire a reference object image, imaging the measurement target object to acquire a target object image, fusing the acquired reference object image and the acquired target object image, and inputting the fused reference object image and target object image to a first neural network model to acquire size information of the measurement target object from the first neural network model.

Abstract: A semiconductor package includes a plurality of semiconductor chips bonded to each other through direct bonding, the plurality of semiconductor chips including a first semiconductor chip and a second semiconductor chip. The first semiconductor chip including: a front insulating layer bonded to a back insulating layer of the second semiconductor chip; a front pad surrounded by the front insulating layer; a device layer on a back surface of the front insulating layer and including an interconnection structure electrically connected to the front pad; a conductive pattern between the interconnection structure and the front pad; and a support insulating layer between the device layer and the front insulating layer and surrounding the conductive pattern, wherein a gap is between a first side surface of the support insulating layer and a second side surface of the conductive pattern that faces the first side surface.

Abstract: A semiconductor package includes a lower structure and an upper structure on the lower structure. The lower structure includes a first substrate, a first through-electrode penetrating the first substrate in a first direction, a first pad connected to the first through-electrode, and a first protective layer surrounding the first pad. The upper structure includes a second substrate, a second through-electrode penetrating the second substrate in the first direction, a second pad connected to the second through-electrode, and a second protective layer surrounding the second pad. The second pad is offset from the first pad in a second direction crossing the first direction. The first pad has a first portion not overlapping the second pad. A first barrier pattern is disposed between the first portion and the second protective layer. A portion of the first barrier pattern is disposed between the first pad and the second pad.

Abstract: A semiconductor package includes a first die having signal and dummy regions, and a second die on the first die. The first die includes first dummy patterns arranged in a first direction on the dummy region, second dummy patterns on the dummy region and between the first dummy patterns, a first dielectric layer on the first and second dummy patterns, and first pads extending through the first dielectric layer and coupled to the first dummy patterns. The second die includes second pads on the dummy region, and third pads on the dummy region. On an interface between the first and second dies, the first pads are in contact with the second pads. The first dielectric layer is between the second dummy patterns and the third pads. The first dummy patterns are connected to a ground circuit or power circuit of the first die.

Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor layer, a first through-electrode passing through the first semiconductor layer in a vertical direction, and a first bonding pad connected to the first through-electrode, and a second semiconductor chip including a second semiconductor layer on the first semiconductor chip, a wiring structure between the second semiconductor layer and the first semiconductor chip, a wiring pad connected to the wiring structure below the wiring structure, and a second bonding pad connected to the wiring pad below the wiring pad and in contact with the first bonding pad, wherein the second bonding pad includes a protrusion protruding toward the wiring pad.

Abstract: The hierarchical occlusion inference method according to the exemplary embodiment of the present disclosure includes: deriving a bounding box feature of the object instance by receiving a region of interest color-depth FPN feature and the object region of interest feature derived from a cluttered scene image including at least one object instance, deriving a visible feature of the object instance by fusing the object region of interest feature and the bounding box feature, deriving an amodal feature of the object instance by fusing the object region of interest feature, the bounding box feature, and the visible feature, deriving an occlusion feature of the object instance by fusing the object region of interest feature, the bounding box feature, the visible feature, and the amodal feature, and inferring occlusion of an object instance by de-convoluting the occlusion feature of the object instance.

Abstract: Provided are a method and electronic device for identifying a size of a measurement target object. The method includes imaging a reference object, which is a reference for identifying the size of the measurement target object, to acquire a reference object image, imaging the measurement target object to acquire a target object image, fusing the acquired reference object image and the acquired target object image, and inputting the fused reference object image and target object image to a first neural network model to acquire size information of the measurement target object from the first neural network model.