Abstract: The present disclosure relates to a display device, and more particularly, to a display device capable of improving color gamut and minimizing a thickness of a filling layer, and an optical device including the same. The display device includes a substrate; a transistor disposed on the substrate; a pixel electrode connected to the transistor; a light emitting layer disposed on the pixel electrode; a common electrode disposed on the light emitting layer; a color filter disposed on the common electrode; a lens disposed on the color filer; and a filling layer disposed on the lens, wherein the color filter and the lens are in direct contact with each other.

Abstract: A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.

Abstract: A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.

Abstract: A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.

Abstract: A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.

Abstract: A non-volatile memory device including: a memory cell array including non-volatile memory blocks connected to a plurality of word lines, a plurality of bit lines and a common source line; a common source line driver configured to supply a common source line voltage to the common source line; a page buffer unit configured to supply a bit line voltage to at least one of the plurality of bit lines; a control logic circuit configured to adjust the common source line voltage and the bit line voltage; and a channel initialization circuit, wherein the channel initialization circuit sets the common source line voltage and the bit line voltage to an initialization pulse, and the channel initialization circuit applies the initialization pulse between a plurality of read sections in which a read voltage is applied to at least two of the plurality of word lines.

Abstract: A non-volatile memory device including: a memory cell array including non-volatile memory blocks connected to a plurality of word lines, a plurality of bit lines and a common source line; a common source line driver configured to supply a common source line voltage to the common source line; a page buffer unit configured to supply a bit line voltage to at least one of the plurality of bit lines; a control logic circuit configured to adjust the common source line voltage and the bit line voltage; and a channel initialization circuit, wherein the channel initialization circuit sets the common source line voltage and the bit line voltage to an initialization pulse, and the channel initialization circuit applies the initialization pulse between a plurality of read sections in which a read voltage is applied to at least two of the plurality of word lines.

Abstract: The present invention relates to a roller shutter in which a slat connection structure is very flexible so as to reduce manufacturing and maintenance costs. The roller shutter of the present invention comprises: a plurality of slats continuously connected in the vertical direction; a winding unit for winding or unwinding the plurality of slats in the vertical direction; a shutter box arranged above a door frame of a building; and a guide frame for guiding the edges of the plurality of slats. The winding unit is arranged inside the shutter box. The plurality of slats are connected in the vertical direction such that the slats can be pivoted. One end of each slat has a hook, and the hook is curved with a predetermined radius of curvature. The other end of each slat has an accommodation groove curved at a predetermined radius of curvature.

Abstract: The present invention relates to a roller shutter in which a slat connection structure is very flexible so as to reduce manufacturing and maintenance costs. The roller shutter of the present invention comprises: a plurality of slats continuously connected in the vertical direction; a winding unit for winding or unwinding the plurality of slats in the vertical direction; a shutter box arranged above a door frame of a building; and a guide frame for guiding the edges of the plurality of slats. The winding unit is arranged inside the shutter box. The plurality of slats are connected in the vertical direction such that the slats can be pivoted. One end of each slat has a hook, and the hook is curved with a predetermined radius of curvature. The other end of each slat has an accommodation groove curved at a predetermined radius of curvature.