Patents by Inventor Rafael Escovar
Rafael Escovar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10579482Abstract: The invention relates to a method of checkpointing the working environment of a user (7) session on a server (1) comprising a first step (11) of checkpointing the working environment of a first application of said session, characterized in that it comprises at least one second step (12) of checkpointing the working environment of a second application of said session different from said first application, and in that said first checkpointing step (11) and said second checkpointing step (12) are synchronized with each other such that the checkpointed working environment of the first application and the checkpointed working environment of the second application are coherent with each other.Type: GrantFiled: July 19, 2016Date of Patent: March 3, 2020Assignee: BULL SASInventors: Sylvain Cohard, Rafael Escovar
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Publication number: 20170024289Abstract: The invention relates to a method of checkpointing the working environment of a user (7) session on a server (1) comprising a first step (11) of checkpointing the working environment of a first application of said session, characterized in that it comprises at least one second step (12) of checkpointing the working environment of a second application of said session different from said first application, and in that said first checkpointing step (11) and said second checkpointing step (12) are synchronized with each other such that the checkpointed working environment of the first application and the checkpointed working environment of the second application are coherent with each other.Type: ApplicationFiled: July 19, 2016Publication date: January 26, 2017Applicant: BULL SASInventors: Sylvain Cohard, Rafael Escovar
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Patent number: 8826204Abstract: Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for instance, a circuit description indicative of the layout of signal wires and ground wires in the circuit is received. The signal wires and the ground wires are grouped into at least a first bundle and a second bundle, wherein the first bundle and the second bundle each comprise a respective signal-wire segment and one or more corresponding ground-wire segments. A representative dipole moment is calculated for the first bundle. Using the representative dipole moment, the mutual inductance between the first bundle and the second bundle is calculated. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing design databases created or modified using any of the disclosed techniques are also disclosed.Type: GrantFiled: September 30, 2013Date of Patent: September 2, 2014Assignee: Mentor Graphics CorporationInventors: Roberto Suaya, Rafael Escovar, Salvador Ortiz
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Patent number: 8667446Abstract: Exemplary impedance extraction methods, systems, and apparatus are described herein. In one exemplary embodiment, for instance, a signal-wire segment of a circuit layout is selected. A predetermined number of return paths are identified for the selected signal-wire segment. The selected signal-wire segment and the identified return paths are further segmented into a plurality of bundles, which comprise signal-wire subsegments and one or more associated return-path subsegments that are parallel to and have the same length as the signal-wire subsegments. Loop inductance values and loop resistance values are determined and stored for the signal-wire subsegments in the bundles for at least one frequency of operation. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing data or information created or modified using any of the disclosed techniques are also disclosed.Type: GrantFiled: March 29, 2010Date of Patent: March 4, 2014Assignee: Mentor Graphics CorporationInventors: Roberto Suaya, Rafael Escovar, Shrinath Thelapurath, Salvador Ortiz, Dusan Petranovic
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Patent number: 8650522Abstract: Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for example, circuit design information indicative of a first inductor and a second inductor is received. A dipole moment associated with the first inductor is determined, where the magnetic field associated with the dipole moment is representative of magnetic fields created by respective turns in the first inductor. A mutual inductance between the first inductor and the second inductor is determined by determining a magnetic flux of the magnetic field of the dipole moment through surfaces bounded by respective wire segments of the second inductor.Type: GrantFiled: April 16, 2012Date of Patent: February 11, 2014Assignee: Mentor Graphics CorporationInventors: Roberto Suaya, Rafael Escovar, Salvador Ortiz
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Publication number: 20140033164Abstract: Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for instance, a circuit description indicative of the layout of signal wires and ground wires in the circuit is received. The signal wires and the ground wires are grouped into at least a first bundle and a second bundle, wherein the first bundle and the second bundle each comprise a respective signal-wire segment and one or more corresponding ground-wire segments. A representative dipole moment is calculated for the first bundle. Using the representative dipole moment, the mutual inductance between the first bundle and the second bundle is calculated. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing design databases created or modified using any of the disclosed techniques are also disclosed.Type: ApplicationFiled: September 30, 2013Publication date: January 30, 2014Applicant: Mentor Graphics CorporationInventors: Roberto Suaya, Rafael Escovar, Salvador Ortiz
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Patent number: 8549449Abstract: Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for instance, a circuit description indicative of the layout of signal wires and ground wires in the circuit is received. The signal wires and the ground wires are grouped into at least a first bundle and a second bundle, wherein the first bundle and the second bundle each comprise a respective signal-wire segment and one or more corresponding ground-wire segments. A representative dipole moment is calculated for the first bundle. Using the representative dipole moment, the mutual inductance between the first bundle and the second bundle is calculated. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing design databases created or modified using any of the disclosed techniques are also disclosed.Type: GrantFiled: February 23, 2009Date of Patent: October 1, 2013Assignee: Mentor Graphics CorporationInventors: Roberto Suaya, Rafael Escovar, Salvador Ortiz
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Publication number: 20120204139Abstract: Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for example, circuit design information indicative of a first inductor and a second inductor is received. A dipole moment associated with the first inductor is determined, where the magnetic field associated with the dipole moment is representative of magnetic fields created by respective turns in the first inductor. A mutual inductance between the first inductor and the second inductor is determined by determining a magnetic flux of the magnetic field of the dipole moment through surfaces bounded by respective wire segments of the second inductor.Type: ApplicationFiled: April 16, 2012Publication date: August 9, 2012Inventors: Roberto Suaya, Rafael Escovar, Salvador Ortiz
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Patent number: 8161438Abstract: Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for example, circuit design information indicative of a first inductor and a second inductor is received. A dipole moment associated with the first inductor is determined, where the magnetic field associated with the dipole moment is representative of magnetic fields created by respective turns in the first inductor. A mutual inductance between the first inductor and the second inductor is determined by determining a magnetic flux of the magnetic field of the dipole moment through surfaces bounded by respective wire segments of the second inductor.Type: GrantFiled: May 16, 2006Date of Patent: April 17, 2012Assignee: Mentor Graphics CorporationInventors: Roberto Suaya, Rafael Escovar, Salvador Ortiz
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Patent number: 8091054Abstract: A method of optimizing the signal propagation speed on a wiring layout is provided. In general, the method accounts for and uses inductance effects caused by the propagation of a high-speed signal on a signal wire surrounded by parallel ground wires. In particular, one of the physical parameters defining the wiring layout may be adjusted to create an rlc relationship in the wiring layout that maximizes the signal propagation speed. The physical parameter that is adjusted may be, for example, the wire separation between the signal wire and the ground wires or the width of the ground wires. The disclosed method may also be applied to a wiring layout having multiple branches, such as a clock tree. In this context, a first branch may be optimized using the disclosed method. Downstream branches may then be adjusted so that the impedances at the junction between the branches are substantially equal.Type: GrantFiled: September 15, 2008Date of Patent: January 3, 2012Assignee: Mentor Graphics CorporationInventors: Roberto Suaya, Rafael Escovar
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Publication number: 20100251191Abstract: Exemplary impedance extraction methods, systems, and apparatus are described herein. In one exemplary embodiment, for instance, a signal-wire segment of a circuit layout is selected. A predetermined number of return paths are identified for the selected signal-wire segment. The selected signal-wire segment and the identified return paths are further segmented into a plurality of bundles, which comprise signal-wire subsegments and one or more associated return-path subsegments that are parallel to and have the same length as the signal-wire subsegments. Loop inductance values and loop resistance values are determined and stored for the signal-wire subsegments in the bundles for at least one frequency of operation. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing data or information created or modified using any of the disclosed techniques are also disclosed.Type: ApplicationFiled: March 29, 2010Publication date: September 30, 2010Inventors: Roberto Suaya, Rafael Escovar, Shrinath Thelapurath, Salvador Ortiz, Dusan Petranovic
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Patent number: 7689962Abstract: Exemplary impedance extraction methods, systems, and apparatus are described herein. In one exemplary embodiment, for instance, a signal-wire segment of a circuit layout is selected. A predetermined number of return paths are identified for the selected signal-wire segment. The selected signal-wire segment and the identified return paths are further segmented into a plurality of bundles, which comprise signal-wire subsegments and one or more associated return-path subsegments that are parallel to and have the same length as the signal-wire subsegments. Loop inductance values and loop resistance values are determined and stored for the signal-wire subsegments in the bundles for at least one frequency of operation. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing data or information created or modified using any of the disclosed techniques are also disclosed.Type: GrantFiled: February 8, 2007Date of Patent: March 30, 2010Inventors: Roberto Suaya, Rafael Escovar, Shrinath Thelapurath, Salvador Ortiz, Dusan Petranovic
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Publication number: 20090172613Abstract: Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for instance, a circuit description indicative of the layout of signal wires and ground wires in the circuit is received. The signal wires and the ground wires are grouped into at least a first bundle and a second bundle, wherein the first bundle and the second bundle each comprise a respective signal-wire segment and one or more corresponding ground-wire segments. A representative dipole moment is calculated for the first bundle. Using the representative dipole moment, the mutual inductance between the first bundle and the second bundle is calculated. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing design databases created or modified using any of the disclosed techniques are also disclosed.Type: ApplicationFiled: February 23, 2009Publication date: July 2, 2009Inventors: Roberto Suaya, Rafael Escovar, Salvador Ortiz
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Patent number: 7496871Abstract: Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for instance, a circuit description indicative of the layout of signal wires and ground wires in the circuit is received. The signal wires and the ground wires are grouped into at least a first bundle and a second bundle, wherein the first bundle and the second bundle each comprise a respective signal-wire segment and one or more corresponding ground-wire segments. A representative dipole moment is calculated for the first bundle. Using the representative dipole moment, the mutual inductance between the first bundle and the second bundle is calculated. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing design databases created or modified using any of the disclosed techniques are also disclosed.Type: GrantFiled: October 21, 2004Date of Patent: February 24, 2009Inventors: Roberto Suaya, Rafael Escovar, Salvador Ortiz
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Publication number: 20090013300Abstract: A method of optimizing the signal propagation speed on a wiring layout is provided. In general, the method accounts for and uses inductance effects caused by the propagation of a high-speed signal on a signal wire surrounded by parallel ground wires. In particular, one of the physical parameters defining the wiring layout may be adjusted to create an rlc relationship in the wiring layout that maximizes the signal propagation speed. The physical parameter that is adjusted may be, for example, the wire separation between the signal wire and the ground wires or the width of the ground wires. The disclosed method may also be applied to a wiring layout having multiple branches, such as a clock tree. In this context, a first branch may be optimized using the disclosed method. Downstream branches may then be adjusted so that the impedances at the junction between the branches are substantially equal.Type: ApplicationFiled: September 15, 2008Publication date: January 8, 2009Inventors: Roberto Suaya, Rafael Escovar
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Patent number: 7454300Abstract: Exemplary impedance extraction methods, systems, and apparatus are described herein. In one exemplary embodiment, at least a portion of a circuit description indicative of a circuit layout is loaded. A signal-wire segment is selected. Loop inductance values and loop resistance values for the signal-wire segment are determined at at least a first frequency of operation and a second frequency of operation. Values for one or more inductance components and one or more resistance components of a broadband representation of the signal-wire segment are computed and stored. In this embodiment, the broadband representation comprises at least one but no more than two parallel-coupled resistance components and inductance components. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing data or information created or modified using any of the disclosed techniques are also disclosed.Type: GrantFiled: February 8, 2007Date of Patent: November 18, 2008Inventors: Roberto Suaya, Rafael Escovar, Shrinath Thelapurath, Salvador Ortiz
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Patent number: 7426706Abstract: A method of optimizing the signal propagation speed on a wiring layout is provided. In general, the method accounts for and uses inductance effects caused by the propagation of a high-speed signal on a signal wire surrounded by parallel ground wires. In particular, one of the physical parameters defining the wiring layout may be adjusted to create an rlc relationship in the wiring layout that maximizes the signal propagation speed. The physical parameter that is adjusted may be, for example, the wire separation between the signal wire and the ground wires or the width of the ground wires. The disclosed method may also be applied to a wiring layout having multiple branches, such as a clock tree. In this context, a first branch may be optimized using the disclosed method. Downstream branches may then be adjusted so that the impedances at the junction between the branches are substantially equal.Type: GrantFiled: February 21, 2006Date of Patent: September 16, 2008Inventors: Roberto Suaya, Rafael Escovar
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Publication number: 20070225925Abstract: Exemplary impedance extraction methods, systems, and apparatus are described herein. In one exemplary embodiment, at least a portion of a circuit description indicative of a circuit layout is loaded. A signal-wire segment is selected. Loop inductance values and loop resistance values for the signal-wire segment are determined at at least a first frequency of operation and a second frequency of operation. Values for one or more inductance components and one or more resistance components of a broadband representation of the signal-wire segment are computed and stored. In this embodiment, the broadband representation comprises at least one but no more than two parallel-coupled resistance components and inductance components. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing data or information created or modified using any of the disclosed techniques are also disclosed.Type: ApplicationFiled: February 8, 2007Publication date: September 27, 2007Inventors: Roberto Suaya, Rafael Escovar, Shrinath Thelapurath, Salvador Ortiz
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Publication number: 20070226659Abstract: Exemplary impedance extraction methods, systems, and apparatus are described herein. In one exemplary embodiment, for instance, a signal-wire segment of a circuit layout is selected. A predetermined number of return paths are identified for the selected signal-wire segment. The selected signal-wire segment and the identified return paths are further segmented into a plurality of bundles, which comprise signal-wire subsegments and one or more associated return-path subsegments that are parallel to and have the same length as the signal-wire subsegments. Loop inductance values and loop resistance values are determined and stored for the signal-wire subsegments in the bundles for at least one frequency of operation. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing data or information created or modified using any of the disclosed techniques are also disclosed.Type: ApplicationFiled: February 8, 2007Publication date: September 27, 2007Inventors: Roberto Suaya, Rafael Escovar, Shrinath Thelapurath, Salvador Ortiz, Dusan Petranovic
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Publication number: 20060282492Abstract: Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for example, circuit design information indicative of a first inductor and a second inductor is received. A dipole moment associated with the first inductor is determined, where the magnetic field associated with the dipole moment is representative of magnetic fields created by respective turns in the first inductor. A mutual inductance between the first inductor and the second inductor is determined by determining a magnetic flux of the magnetic field of the dipole moment through surfaces bounded by respective wire segments of the second inductor.Type: ApplicationFiled: May 16, 2006Publication date: December 14, 2006Inventors: Roberto Suaya, Rafael Escovar, Salvador Ortiz