Abstract: A read only memory (ROM) which is made up of an array and a current sensing circuit. The array is made up of a number of cells each cell being adapted for storing N bits. Each cell has an operative element which is of one of 2N sizes representative of a combination of N bits. The current sensing circuit is connected to the array and senses the size of the operative elements of the array. The current sensing circuit thus differentiates between the 2N sizes of the operative elements to determine the values of each bit of the N bits in each cell. N is an integer greater than 1.

Abstract: A static pass-transistor logic gate design which incorporates the new technique of forecasted-restoration of the output logic-level. The forecasting of the need for output logic-level restoration is accomplished by the connection of restoration circuit inputs to a logic-gate input, which provides the appropriate logic input signal to the restoration circuit, to properly control the state of the restoration circuit. Logic gate inputs which are unnecessary in the determine of the appropriate restoration circuit input logic state are connected to the appropriate input logic levels. Further, there is potential for significant area savings, with accompanying economic benefit when using the FRCPG logic, due to the reduced transistor count of FRCPG.

Abstract: Reflections and cross talk in a high-speed, bidirectional transmission line are minimized by terminating the transmission line with a network including a "serial" resistor connected in series between an end of the transmission line and a parallel (e.g. data) port, a "pull-up" resistor connected to the transmission line side of the serial resistor, and a capacitor connected between the parallel port side of the serial resistor and ground. Optionally, a diode is connected between the pull-up resistor and a bias potential. A variety of exemplary values for these components (i.e., serial resistor, pull-up resistor, capacitor) are discussed, in the context of particular signals. Preferably, the capacitor and the resistors are positioned as close as possible to the connector.

Abstract: A protection system for an integrated circuit includes a protection structure for the input terminals and output terminals that protects against ESD stress in bonding pad to V.sub.SS and bonding pad to V.sub.DD paths, both negative and positive paths. The protection system also includes a protection structure for protecting bonding pad to bonding pad electrical paths and a protection structure for V.sub.DD to V.sub.SS paths. Using all three protection structures in combination provides full protection against ESD events in all possible paths in an integrated circuit. A protection structure isolates an output buffer from the protection structure and encourages stress discharge through the protection structure rather than the output buffer.

Abstract: An accurate peak-to-peak detector, readily implemented in CMOS and consuming low power. The peak-to-peak detector includes a clamp portion (circuit) followed by a peak-detect portion (circuit), each of which circuits includes at least one active component (e.g., transistor). The clamp circuit receives an input signal having an alternating current (AC) component via an input coupling capacitor which outputs a voltage on a line to the peak-detect circuit. The clamp circuit includes either a passive load element (e.g., a resistor), or an active load element (e.g., a CMOS transistor), so that the clamp circuit bleeds current from the input coupling capacitor, and any slow drift in the DC level of the input voltage will be followed. The peak-detect circuit follows the voltage output by the coupling capacitor, and includes either a passive load element (e.g., a resistor) or an active load element (e.g.

Abstract: A frequency multiplier circuit generates an supplemental high-frequency timing signal from a single, low-frequency current-controlled oscillator (CCO). The current-controlled oscillator (CCO) generates a controlled discharge current and a controlled bias current which are controlled in parallel to substantially eliminate inaccuracies in a characteristic frequency-current curve of the current-controlled oscillator. The frequency multiplier circuit generates a high-frequency timing signal using the digitally-controlled CCO and avoids the usage of a phase-locked loop (PLL) technique. Specifically, a frequency multiplier includes a current-controlled oscillator having a plurality of input lines connected to receive a digital current select signal and having an output terminal connected to carry a timing signal at a current-controlled oscillator frequency f.sub.CCO set in accordance with the current select signal.

Abstract: A phase-locked loop circuit and method for producing an output signal which is phase locked with respect to an input signal are disclosed. The circuit includes a phase detector responsive to the phase relationship between the input signal and the output signal. A controlled signal generator, which includes a voltage controlled oscillator, generates the output signal and includes coarse adjust circuitry and fine adjust circuitry. The coarse adjust circuitry causes the frequency of the output signal to fall within one of a selected group of frequency bands in response to the frequency of the input signal. Once the coarse adjustment is made, the fine adjust circuitry continuously changes the frequency and phase of the output signal in response to the phase detector so that the output signal will be phase locked to the input signal.