Patents by Inventor Rafael G. Cabezas
Rafael G. Cabezas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9298568Abstract: The present invention provides a computer implemented method, data processing system and computer program product for running a diagnostic test on an I/O adapter. The data processing system communicates a stop command to a functional device driver; wherein the functional device driver is configured to communicate with the I/O adapter. The data processing system determines whether the functional device driver has completed storing a state of the I/O adapter. The data processing system loads a diagnostic device driver for communicating with the I/O adapter. The data processing system applies test inputs to the diagnostic device driver, wherein at least one test input is presented to the I/O adapter. The data processing system receives test results from the diagnostic device driver.Type: GrantFiled: February 7, 2008Date of Patent: March 29, 2016Assignee: International Business Machines CorporationInventors: Rafael G. Cabezas, Anh T. Dang, Brandon D. Nelson
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Patent number: 8347142Abstract: A primary I/O adapter and a redundant I/O adapter of a data processing system are assigned to support access to a system resource. While the primary I/O adapter is in service and the redundant I/O adapter is not in service in providing access to the system resource, a fail over command is issued to remove the primary I/O adapter from service and place the redundant I/O adapter in service in supporting access to the system resource. While the redundant I/O adapter is in service and the primary I/O adapter is not in service in providing access to the system resource, diagnostic testing on the primary I/O adapter is performed. In response to the diagnostic testing revealing no fault in the primary I/O adapter, a fail back command is issued to restore the primary I/O adapter to service and to remove the redundant I/O adapter from service.Type: GrantFiled: March 17, 2011Date of Patent: January 1, 2013Assignee: International Business Machines CorporationInventors: Rafael G. Cabezas, David D. Galvin, Binh K. Hua, Sivarama K. Kodukula
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Patent number: 8006133Abstract: A primary I/O adapter and a redundant I/O adapter of a data processing system are assigned to support access to a system resource. While the primary I/O adapter is in service and the redundant I/O adapter is not in service in providing access to the system resource, a fail over command is issued to remove the primary I/O adapter from service and place the redundant I/O adapter in service in supporting access to the system resource. While the redundant I/O adapter is in service and the primary I/O adapter is not in service in providing access to the system resource, diagnostic testing on the primary I/O adapter is performed. In response to the diagnostic testing revealing no fault in the primary I/O adapter, a fail back command is issued to restore the primary I/O adapter to service and to remove the redundant I/O adapter from service.Type: GrantFiled: February 14, 2008Date of Patent: August 23, 2011Assignee: International Business Machines CorporationInventors: Rafael G. Cabezas, David D. Galvin, Binh K. Hua, Sivarama K. Kodukula
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Publication number: 20110167293Abstract: A primary I/O adapter and a redundant I/O adapter of a data processing system are assigned to support access to a system resource. While the primary I/O adapter is in service and the redundant I/O adapter is not in service in providing access to the system resource, a fail over command is issued to remove the primary I/O adapter from service and place the redundant I/O adapter in service in supporting access to the system resource. While the redundant I/O adapter is in service and the primary I/O adapter is not in service in providing access to the system resource, diagnostic testing on the primary I/O adapter is performed. In response to the diagnostic testing revealing no fault in the primary I/O adapter, a fail back command is issued to restore the primary I/O adapter to service and to remove the redundant I/O adapter from service.Type: ApplicationFiled: March 17, 2011Publication date: July 7, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: RAFAEL G. CABEZAS, DAVID D. GALVIN, BINH K. HUA, SIVARAMA K. KODUKULA
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Publication number: 20090276793Abstract: The present invention provides a computer implemented method, data processing system and computer program product for running a diagnostic test on an I/O adapter. The data processing system communicates a stop command to a functional device driver; wherein the functional device driver is configured to communicate with the I/O adapter. The data processing system determines whether the functional device driver has completed storing a state of the I/O adapter. The data processing system loads a diagnostic device driver for communicating with the I/O adapter. The data processing system applies test inputs to the diagnostic device driver, wherein at least one test input is presented to the I/O adapter. The data processing system receives test results from the diagnostic device driver.Type: ApplicationFiled: February 7, 2008Publication date: November 5, 2009Inventors: Rafael G. Cabezas, Anh T. Dang, Brandon D. Nelson
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Publication number: 20090210751Abstract: A primary I/O adapter and a redundant I/O adapter of a data processing system are assigned to support access to a system resource. While the primary I/O adapter is in service and the redundant I/O adapter is not in service in providing access to the system resource, a fail over command is issued to remove the primary I/O adapter from service and place the redundant I/O adapter in service in supporting access to the system resource. While the redundant I/O adapter is in service and the primary I/O adapter is not in service in providing access to the system resource, diagnostic testing on the primary I/O adapter is performed. In response to the diagnostic testing revealing no fault in the primary I/O adapter, a fail back command is issued to restore the primary I/O adapter to service and to remove the redundant I/O adapter from service.Type: ApplicationFiled: February 14, 2008Publication date: August 20, 2009Inventors: Rafael G. Cabezas, David D. Galvin, Binh K. Hua, Sivarama K. Kodukula
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Patent number: 7085939Abstract: A method and apparatus for handling power consumption of a bus-controlled component such that the power requirements of the bus-controlled component are met without drawing excessive power from the computer bus. The apparatus of the present invention includes two embodiment of a bus power handling device that enables power to be obtained directly from a power supply and from a bus slot. In a first embodiment, the bus power handling device fits between the bus slot and the bus-controlled component and enable the component to obtain power directly from a power supply and from the bus slot. In a second embodiment, the bus power handling device is located on the bus-controlled component and allows connection to the power supply and the bus slot. The method of the present invention includes a technique to draw additional power required for the bus-controlled component directly from a power supply.Type: GrantFiled: December 14, 2000Date of Patent: August 1, 2006Assignee: International Business Machines CorporationInventors: Rafael G. Cabezas, Daniel J. Knabenbauer
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Patent number: 6980947Abstract: An evaluation system and method for computer products that uses a unified diagnostics platform having a switching multiplexor to generate a plurality of computer systems and computer environments. The evaluation system of the present invention includes a unified diagnostics platform that facilitates a variety of different computer systems by connecting computer peripherals, processors and operating systems. The switching multiplexor may be a plurality of switches allowing multiple combinations and configurations of devices connected to the unified diagnostics platform. The switching multiplexor is controlled using a controller that may be a hardware or a software selector. The evaluation method of the present invention includes a method for evaluating a computer product on a plurality of computer systems using the unified diagnostics platform.Type: GrantFiled: July 12, 2001Date of Patent: December 27, 2005Assignee: International Business Machines CorporationInventors: Rafael G. Cabezas, Daniel J. Knabenbauer
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Publication number: 20040210777Abstract: A method and apparatus for handling power consumption of a bus-controlled component such that the power requirements of the bus-controlled component are met without drawing excessive power from the computer bus. The apparatus of the present invention includes two embodiment of a bus power handling device that enables power to be obtained directly from a power supply and from a bus slot. In a first embodiment, the bus power handling device fits between the bus slot and the bus-controlled component and enable the component to obtain power directly from a power supply and from the bus slot. In a second embodiment, the bus power handling device is located on the bus-controlled component and allows connection to the power supply and the bus slot. The method of the present invention includes a technique to draw additional power required for the bus-controlled component directly from a power supply.Type: ApplicationFiled: December 14, 2000Publication date: October 21, 2004Applicant: International Business Machines CorporationInventors: Rafael G. Cabezas, Daniel J. Knabenbauer
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Patent number: 6745345Abstract: A method for testing a computer bus using a bridge chip having a freeze-on-error option that enables a computer system's central processing unit (CPU) to recover and continue processing even when the computer bus is not functional. The testing method of the present invention remains transparent to a user and can be accomplished while performing standard diagnostics tests. In general, the present invention injects an input/output (I/O) error into a specific bus slot of the computer bus to test the functionality (such as the error recovery capability) of the bus. The present invention then recovers from the failure condition without having the computer system shutdown or stop working and without having to restart the computer system. More specifically, the method for testing a computer bus according to the present invention includes enabling the freeze-on-error option on the bridge chip, injecting an error into the specified computer bus slot and recovering from the injected error.Type: GrantFiled: December 4, 2000Date of Patent: June 1, 2004Assignee: International Business Machines CorporationInventors: Rafael G. Cabezas, Dhirendra Dhopeshwarkar, Robert G. Kovacs, Arthur J. Tysor
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Publication number: 20030014618Abstract: An evaluation system and method for computer products that uses a unified diagnostics platform having a switching multiplexor to generate a plurality of computer systems and computer environments. The evaluation system of the present invention includes a unified diagnostics platform that facilitates a variety of different computer systems by connecting computer peripherals, processors and operating systems. The switching multiplexor may be a plurality of switches allowing multiple combinations and configurations of devices connected to the unified diagnostics platform. The switching multiplexor is controlled using a controller that may be a hardware or a software selector. The evaluation method of the present invention includes a method for evaluating a computer product on a plurality of computer systems using the unified diagnostics platform.Type: ApplicationFiled: July 12, 2001Publication date: January 16, 2003Applicant: International Business Machines CorporationInventors: Rafael G. Cabezas, Daniel J. Knabenbauer
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Publication number: 20020095624Abstract: A method for testing a computer bus using a bridge chip having a freeze-on-error option that enables a computer system's central processing unit (CPU) to recover and continue processing even when the computer bus is not functional. The teeting method of the present invention remains transparent to a user and can be accomplished while performing standard diagnostics tests. In general, the present invention injects an input/output (I/O) error into a specific bus slot of the computer bus to test the functionality (such as the error recovery capability) of the bus. The present invention then recovers from the failure condition without having the computer system shutdown or stop working and without having to restart the computer system. More specifically, the method for testing a computer bus according to the present invention includes enabling the freeze-on-error option on the bridge chip, injecting an error into the specified computer bus slot and recovering from the injected error.Type: ApplicationFiled: December 4, 2000Publication date: July 18, 2002Applicant: International Business Machines CorporationInventors: Rafael G. Cabezas, Dhirendra Dhopeshwarkar, Robert G. Kovacs, Arthur J. Tysor
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Patent number: 5612961Abstract: A method of verifying the baud rate for communication of data by an Asynchronous serial device residing within a data processing system. The data processing system having a first Asynchronous serial device and a second Asynchronous serial device. The first and second serial devices are connected one to another for communication of data therebetween. The first and second serial devices are initialized with a common baud rate for transmission and reception of data, respectively. A test sequence pattern is created, and transmitted at the common baud rate from the first serial device to the second serial device. The second serial device transmits the received test sequence pattern back to the first serial device. The test sequence pattern is then verified as either valid or invalid.Type: GrantFiled: April 27, 1995Date of Patent: March 18, 1997Assignee: International Business Machines CorporationInventors: Rafael G. Cabezas, Richard A. Foster