Abstract: A verification support apparatus includes an identifying unit that, by using a pre-change specification and a post-change specification given before and after a specification change in a subject to be verified, identifies an area that has changed from among a plurality of specification items included in the post-change specification and a selecting unit that selects a specification item from among the areas identified by the identifying unit. The verification support apparatus further includes a searching unit that, by referring a transition graph concerning the specification items included in the post-change specification and by tracing specification items as origins of transitions from a starting point that is the specification item selected by the selecting unit, searches for a route made up of specification items affected by the specification change; and an output unit that outputs a search result of the searching unit.

Abstract: In a design verification apparatus, a priority resolver selects one or more verification datasets for verifying a procedure described in a design specification of a target product, in response to a verification request for that procedure. The priority resolver determines a priority score of each parameter that the selected verification datasets specify as a constraint on the procedure. A verification order resolver determines a verification order of the selected verification datasets, based on the priority scores determined by the priority resolver. An output processor produces data identifying the verification datasets, together with indication of the determined verification order.

Abstract: Hardware blocks respectively of an arbitrary access origin and an arbitrary access destination that are mutually accessible are extracted from among a plurality of hardware blocks constituting a bus system to be verified, and a path reaching from the access-origin hardware block to the access-destination hardware block is searched for. For each path found, a verification scenario is generated to verify transactions of the access-origin hardware block for a case where access to an address range assigned to the access-destination hardware block occurs, and the verification scenario is output being correlated with the path that corresponds thereto.

Abstract: In a verification supporting apparatus, a recording unit records a DIRW matrix in which a state transition possibly occurring in a register of a circuit to be verified and information concerning validity of a path corresponding to the state transition are set and an acquiring unit acquires a control data flow graph that includes a control flow graph having a data flow graph written therein. When a register is designated for verification, a data flow graph having described therein the designated register is extracted from the control data flow graph. From the data flow graph extracted, a path indicating the flow of data concerning the register is extracted. The state transition of the path extracted is identified and if the state transition is determined to be is set in the DIRW matrix, information concerning the validity set in the DIRW matrix and the path are correlated, and output.

Abstract: A design verification apparatus includes a processor to produce and place constraint conditions on verification datasets provided to verify a first design specification of a target product. The processor produces those constraint conditions from a second design specification of the target product, based on links from units of processing which constitute a procedure defined for each verification item in the second design specification to units of processing in the first design specification. The processor outputs data identifying the resulting verification datasets having the constraint conditions, together with their corresponding verification items.

Abstract: A non-transitory, computer-readable recording medium stores therein a verification program that causes a computer to execute detecting from a structure expressing a group of scenarios for verifying an operation of a design under verification and by hierarchizing sequences for realizing the operation as nodes, a similar node similar to a faulty node representing a sequence in which a fault has occurred; generating a string of sequences represented by a group of nodes on a path starting from a start node of the structure to the detected similar node; and outputting the generated string of sequences.

Abstract: In a design verification apparatus, a priority resolver selects one or more verification datasets for verifying a procedure described in a design specification of a target product, in response to a verification request for that procedure. The priority resolver determines a priority score of each parameter that the selected verification datasets specify as a constraint on the procedure. A verification order resolver determines a verification order of the selected verification datasets, based on the priority scores determined by the priority resolver. An output processor produces data identifying the verification datasets, together with indication of the determined verification order.

Abstract: A design verification apparatus includes a dataset generator to generate verification datasets which associate each unit process of a plurality of procedures (processing scenarios) described in a design specification of a target product with an identifier (label) designating which portion of the design specification is to be verified. A process priority setting unit assigns a process priority to each verification dataset according to specified identifiers. An output processor outputs data identifying the verification datasets, together with explicit indication of their process priorities.

Abstract: A program, an apparatus and a method verify a program that efficiently verifies a concurrent/parallel program, allowing interactively debugging the current/parallel program. The program causes a computer to execute a detection step that detects the function that has been altered and the function that uses a shared variable influenced by the alteration out of the program to be verified before and after the alteration and also detects the part that is influenced by the alteration, the control structure part and the other parts, a model generation step that generates a model on the basis of the outcome of the detection in the detection step and a verification step that verifies the program to be verified after the alteration by comparing the model of the program to be verified before the alteration and the model of the program to be verified after the alteration.

Abstract: A verification assisting apparatus for assisting a matching check between a specification and implementation of an object includes: an obtaining unit that obtains a specification description including elements executed to realize functions of the object and restricting conditions of the elements to realize the functions, and an implementation description concerning the functions; a creating unit that creates a graph structure including, as nodes, the elements and the restricting conditions, based on the implementation description; a first correlating unit that correlates nodes in the graph structure with the implementation description; a second correlating unit that correlates a node in the graph structure with the specification description, by detecting the node in the structure using a description concerning the element or the restricting condition in the specification description; and an outputting unit that outputs the correlation results.

Abstract: In a verification supporting apparatus, a recording unit records a DIRW matrix in which a state transition possibly occurring in a register of a circuit to be verified and information concerning validity of a path corresponding to the state transition are set and an acquiring unit acquires a control data flow graph that includes a control flow graph having a data flow graph written therein. When a register is designated for verification, a data flow graph having described therein the designated register is extracted from the control data flow graph. From the data flow graph extracted, a path indicating the flow of data concerning the register is extracted. The state transition of the path extracted is identified and if the state transition is determined to be is set in the DIRW matrix, information concerning the validity set in the DIRW matrix and the path are correlated, and output.

Abstract: A verification support apparatus includes an identifying unit that, by using a pre-change specification and a post-change specification given before and after a specification change in a subject to be verified, identifies an area that has changed from among a plurality of specification items included in the post-change specification and a selecting unit that selects a specification item from among the areas identified by the identifying unit. The verification support apparatus further includes a searching unit that, by referring a transition graph concerning the specification items included in the post-change specification and by tracing specification items as origins of transitions from a starting point that is the specification item selected by the selecting unit, searches for a route made up of specification items affected by the specification change; and an output unit that outputs a search result of the searching unit.

Abstract: Hardware blocks respectively of an arbitrary access origin and an arbitrary access destination that are mutually accessible are extracted from among a plurality of hardware blocks constituting a bus system to be verified, and a path reaching from the access-origin hardware block to the access-destination hardware block is searched for. For each path found, a verification scenario is generated to verify transactions of the access-origin hardware block for a case where access to an address range assigned to the access-destination hardware block occurs, and the verification scenario is output being correlated with the path that corresponds thereto.

Abstract: There are provided a medium storing a model creation program for creating a model for communicating with an object apparatus to be verified, a model creation apparatus and a model creation method. A medium storing a model creation program for causing a computer to create a model for communicating with an object apparatus to be verified so as to be readable to the computer, wherein the program causes the computer to execute an acquisition step that acquires a first finite state machine expressing the interface specification of the object apparatus to be verified as a finite state machine, a first addition step that adds an error state and a state transition to the error state to the first finite state machine to produce a second finite state machine and sets the transition conditions of the second transition machine according to the set error probability and a conversion step that converts the second finite state machine into a model for communicating with the object apparatus to be verified.

Abstract: The present invention has been made to provide a software verification program, a software verification apparatus, and a software verification method capable of reducing verification cost of concurrent/parallel software. A software verification program allowing a computer to execute verification of software including a library 11 and a program that uses a library 21 to operate in a concurrent or parallel manner, comprises: a shared element utilizing part extraction step that extracts a part at which a shared element, which is an element that is defined in the library 21 and which can be used by the program 22, is used in the program 22; and a condition verification step that verifies based on a thread-safe condition defined in the library 21 for the each shared element whether a shared element in the shared element utilizing part extracted by the shared element utilizing part extraction step satisfies the thread-safe condition.