Abstract: An apparatus for charging in a network environment is provided that includes an access gateway encapsulation/decapsulation element operable to establish one or more packet data protocol (PDP) links on behalf of an end user and to perform encapsulation and decapsulation operations for one or more of the links associated with the end user. The access gateway encapsulation/decapsulation element is further operable to interface with a client services packet gateway (CSPG) that is operable to provide enhanced packet processing for the end user for requested information. The apparatus also includes an access gateway policy element operable to interface with the CSPG. The access gateway encapsulation/decapsulation element and the access gateway policy element cooperate to use one or more inter-module headers in order to coordinate the enhanced packet processing for one or more communication flows associated with the end user.

Abstract: A network buffer memory is divided into pools of locations including a plurality of tinygram contiguous sections and a plurality of jumbogram contiguous sections. The tinygram contiguous sections available for storage of packets are listed in a list of tinygram pointers. The jumbogram contiguous sections available for storage of packets are also listed in a list of jumbogram pointers. A threshold for distinguishing the packets as tinygrams and jumbograms is programmed. As packets are received, they are measured against the threshold. Responsive to detection of an end of packet condition prior to reaching the threshold, storing the packet in a tinygram contiguous section. Otherwise, the packet is stored in a jumbogram contiguous section. Availability of sections is determined by query to the FIFO lists of pointers.

Abstract: A generic high bandwidth adapter providing a unified architecture for data communications between buses, channels, processors, switch fabrics and/or communication networks. Data is carried by data stream packets of variable lengths, and each packet includes a header control information portion required by communication protocols used to mediate the information exchange, and normally a data portion for the data which is to be communicated. A packet memory stores data packets arriving at a plurality of generic adapter input/output ports. The packet memory is segmented into a plurality of buffers, and each data packet is stored in one or more buffers as required by the length thereof.

Abstract: A generic high bandwidth adapter providing a unified architecture for data communications between buses, channels, processors, switch fabrics and/or communication networks. Data is carried by data stream packets of variable lengths, and each packet includes a header control information portion required by communication protocols used to mediate the information exchange, and normally a data portion for the data which is to be communicated. The generic high bandwidth adapter comprises a processor subsystem including a processor for processing the header control information portions of data packets. The processor has access to data packets stored in a packet memory which stores data packets arriving at four generic adapter input/output ports. The packet memory is segmented into a plurality of buffers, and each data packet is stored in one or more buffers as required by the length thereof.