Patents by Inventor Rafael M. VILELA

Rafael M. VILELA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Code coverage circuitry
    Patent number: 9153346
    Abstract: A method with a circuit that includes a memory (130) coupled to an analog line coverage circuit (104). The analog line coverage circuit includes a plurality of buffers (151-154) in which each buffer is coupled to one memory location of the memory, a plurality of bin cells (161-164) in which each bin cell is coupled to a buffer, a multiplexer (170), each input terminal of which is coupled to a bin cell, and an analog-to-digital converter (180) coupled to the multiplexer and to an output terminal of the analog line coverage circuit. The analog line coverage circuit stores an analog voltage that is representative of a number of occasions that a memory location is accessed, and outputs a signal indicative thereof. A processor (102), coupled to the memory and to the analog line coverage circuit, enables the analog line coverage circuit when the processor is in a debug mode.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: October 6, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Rafael M. Vilela, Walter Luis Tercariol, Fernando Zampronho Neto, Sandro A. P. Haddad
  • CODE COVERAGE CIRCUITRY
    Publication number: 20140325297
    Abstract: A method with a circuit that includes a memory (130) coupled to an analog line coverage circuit (104). The analog line coverage circuit includes a plurality of buffers (151-154) in which each buffer is coupled to one memory location of the memory, a plurality of bin cells (161-164) in which each bin cell is coupled to a buffer, a multiplexer (170), each input terminal of which is coupled to a bin cell, and an analog-to-digital converter (180) coupled to the multiplexer and to an output terminal of the analog line coverage circuit. The analog line coverage circuit stores an analog voltage that is representative of a number of occasions that a memory location is accessed, and outputs a signal indicative thereof. A processor (102), coupled to the memory and to the analog line coverage circuit, enables the analog line coverage circuit when the processor is in a debug mode.
    Type: Application
    Filed: July 9, 2014
    Publication date: October 30, 2014
    Inventors: Rafael M. VILELA, Walter Luis TERCARIOL, Fernando Zampronho NETO, Sandro A. P. HADDAD
  • Code coverage circuitry
    Patent number: 8811108
    Abstract: A circuit includes a memory (130) coupled to an analog line coverage circuit (104). The analog line coverage circuit includes a plurality of buffers (151-154) in which each buffer is coupled to one memory location of the memory, a plurality of bin cells (161-164) in which each bin cell is coupled to a buffer, a multiplexer (170), each input terminal of which is coupled to a bin cell, and an analog-to-digital converter (180) coupled to the multiplexer and to an output terminal of the analog line coverage circuit. The analog line coverage circuit stores an analog voltage that is representative of a number of occasions that a memory location is accessed, and outputs a signal indicative thereof. A processor (102) is coupled to the memory and to the analog line coverage circuit, and the processor enables the analog line coverage circuit when the processor is in a debug mode.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: August 19, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Rafael M. Vilela, Walter Luis Tercariol, Fernando Zampronho Neto, Sandro A. P. Haddad
  • CODE COVERAGE CIRCUITRY
    Publication number: 20130033924
    Abstract: A circuit includes a memory (130) coupled to an analog line coverage circuit (104). The analog line coverage circuit includes a plurality of buffers (151-154) in which each buffer is coupled to one memory location of the memory, a plurality of bin cells (161-164) in which each bin cell is coupled to a buffer, a multiplexer (170), each input terminal of which is coupled to a bin cell, and an analog-to-digital converter (180) coupled to the multiplexer and to an output terminal of the analog line coverage circuit. The analog line coverage circuit stores an analog voltage that is representative of a number of occasions that a memory location is accessed, and outputs a signal indicative thereof. A processor (102) is coupled to the memory and to the analog line coverage circuit, and the processor enables the analog line coverage circuit when the processor is in a debug mode.
    Type: Application
    Filed: August 1, 2011
    Publication date: February 7, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Rafael M. VILELA, Walter Luis TERCARIOL, Fernando Zampronho NETO, Sandro A.P. HADDAD