Patents by Inventor Rafael Pena Bello

Rafael Pena Bello has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10019395
    Abstract: The invention provides a processing system, comprising a memory comprising a processor call stack; a stack space usage register configured to determine the stack space usage of the processor call stack and to store a usage parameter indicative of the determined stack space usage; a first threshold register configured to store a pre-determinable first stack level threshold; and a first comparator configured to compare the usage parameter with the first stack level threshold and to output a first interrupt blocking signal, if the usage parameter exceeds the first stack level threshold, the first interrupt blocking signal being configured to block the decoding of interrupt signals input to the processing system and having interrupt priorities lower than or equal to or just lower than a first interrupt priority threshold. The invention further provides a method for stack management, especially in a processing system.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: July 10, 2018
    Assignee: NXP USA, Inc.
    Inventors: Dirk Heisswolf, Andreas Ralph Pachl, Rafael Pena Bello
  • Publication number: 20160292097
    Abstract: The invention provides a processing system, comprising a memory comprising a processor call stack; a stack space usage register configured to determine the stack space usage of the processor call stack and to store a usage parameter indicative of the determined stack space usage; a first threshold register configured to store a pre-determinable first stack level threshold; and a first comparator configured to compare the usage parameter with the first stack level threshold and to output a first interrupt blocking signal, if the usage parameter exceeds the first stack level threshold, the first interrupt blocking signal being configured to block the decoding of interrupt signals input to the processing system and having interrupt priorities lower than or equal to or just lower than a first interrupt priority threshold. The invention further provides a method for stack management, especially in a processing system.
    Type: Application
    Filed: November 8, 2013
    Publication date: October 6, 2016
    Inventors: Dirk HEISSWOLF, Andreas Ralph PACHL, Rafael PENA BELLO
  • Patent number: 8957702
    Abstract: A signalling circuit for a signal channel of a communication network comprises a communication network terminal connectable to the signal channel and to a voltage supply; an input terminal connectable to receive a transmit signal; a driver device comprising a first driver terminal connected to the communication network terminal, a second driver terminal connected to ground, and a driver control terminal connected to the input terminal; wherein the driver device is arranged to connect the communication network terminal to ground in response to a transition from a low to a high voltage driver control signal state of a driver control signal received at the driver control terminal.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: February 17, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mathieu Lesbats, Hubert Bode, Rafael Pena Bello
  • Publication number: 20140169495
    Abstract: A signalling circuit for a signal channel of a communication network comprises a communication network terminal connectable to the signal channel and to a voltage supply; an input terminal connectable to receive a transmit signal; a driver device comprising a first driver terminal connected to the communication network terminal, a second driver terminal connected to ground, and a driver control terminal connected to the input terminal; wherein the driver device is arranged to connect the communication network terminal to ground in response to a transition from a low to a high voltage driver control signal state of a driver control signal received at the driver control terminal.
    Type: Application
    Filed: August 1, 2011
    Publication date: June 19, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Mathieu Lesbats, Hubert Bode, Rafael Pena Bello