Abstract: A data processing apparatus has an instruction memory system arranged to output an instruction word addressed by an instruction address. An instruction execution unit, processes a plurality of instructions from the instruction word in parallel. A detection unit, detects in which of a plurality of ranges the instruction address lies. The detection unit is coupled to the instruction execution unit and/or the instruction memory system, to control a way in which the instruction execution unit parallelizes processing of the instructions from the instruction word, dependent on a detected range. In an embodiment the instruction execution unit and/or the instruction memory system adjusts a width of the instruction word that determines a number of instructions from the instruction word that is processed in parallel, dependent on the detected range.

Abstract: A data processing apparatus has an instruction memory system arranged to output an instruction word addressed by an instruction address. An instruction execution unit, processes a plurality of instructions from the instruction word in parallel. A detection unit, detects in which of a plurality of ranges the instruction address lies. The detection unit is coupled to the instruction execution unit and/or the instruction memory system, to control a way in which the instruction execution unit parallelizes processing of the instructions from the instruction word, dependent on a detected range. In an embodiment the instruction execution unit and/or the instruction memory system adjusts a width of the instruction word that determines a number of instructions from the instruction word that is processed in parallel, dependent on the detected range.

Abstract: A program of instruction words is executed with a VLIW data processing apparatus. The apparatus comprises a plurality of functional units capable of executing a plurality of instructions from each instruction word in parallel. The instructions from each of at least some of the instruction words are fetched from respective memory units in parallel, addressed with an instruction address that is common for the functional units. Translation of the instruction address into a physical address can be modified for one or more particular ones of the memory units. Modification is controlled by modification update instructions in the program. Thus, it can be selected dependent on program execution which instructions from the memory units will be combined into the instruction word in response to the instruction address.

Abstract: A data processing apparatus has an instruction memory system arranged to output an instruction word, capable of containing a plurality of instructions, respective instruction words being output in response to respective instruction addresses. An instruction execution unit contains a plurality of functional units, each capable of executing a respective instruction from the instruction word in parallel with execution of other instructions from the instruction word by other ones of the functional units. A power saving circuit is provided to switch a selectable subset of the functional units and/or parts of the instruction memory to a power saving state, while other functional units and parts of the instruction memory continue processing instructions in a normal power consuming state. The power saving circuit selects the functional units and/or parts of the instruction memory dependent on program execution.

Abstract: The invention relates to a method of controlling decoder drift for memory compression comprising the steps of providing a decoded bit-stream output of a decoder (79) and a bit-stream input to an encoder (76) in a first pass of a coding loop, where the bit-stream input to the encoder (76) is based on the decoded bit-stream output of the decoder (79), determining a difference between the bit-stream input to the encoder (76) and the decoded bit-stream output of the decoder (79), where the difference is due to a compression of the decoded bit-stream output of the decoder (79) in the encoder (76) during the first coding loop and correcting the decoded bit-stream output of the decoder (79) in dependence on the determined difference in a second pass of the coding loop.

Abstract: A data processing apparatus has an instruction memory system arranged to output an instruction word, capable of containing a plurality of instructions, respective instruction words being output in response to respective instruction addresses. An instruction execution unit contains a plurality of functional units, each capable of executing a respective instruction from the instruction word in parallel with execution of other instructions from the instruction word by other ones of the functional units. A power saving circuit is provided to switch a selectable subset of the functional units and/or parts of the instruction memory to a power saving state, while other functional units and parts of the instruction memory continue processing instructions in a normal power consuming state. The power saving circuit selects the functional units and/or parts of the instruction memory dependent on program execution.

Abstract: A method to determine motion vectors for respective segments (S11-S14) of a segmented image (100) comprises: creating sets of candidate motion vectors for the respective segments (S11-S14); dividing the segmented image (100) into a grid of blocks (b11-b88) of pixels; determining for the blocks (b11-b88) of pixels which of the candidate motion vectors belong to the blocks (b11-b88), on basis of the segments (S11-S14) and the locations of the blocks (b11-b88) within the segmented image (100); computing partial match errors for the blocks (b11-b88) on basis of the determined candidate motion vectors and on basis of pixel values of a further image (102); combining the partial match errors into a number of match errors per segment; selecting for each of the sets of candidate motion vectors respective candidate motion vectors on basis of the match errors; and assigning the selected candidate motion vectors as the motion vectors for the respective segments (S11-S14).

Abstract: A data processing apparatus has an instruction memory system arranged to output an instruction word addressed by an instruction address. An instruction execution unit, processes a plurality of instructions from the instruction word in parallel. A detection unit, detects in which of a plurality of ranges the instruction address lies. The detection unit is coupled to the instruction execution unit and/or the instruction memory system, to control a way in which the instruction execution unit parallelizes processing of the instructions from the instruction word, dependent on a detected range. In an embodiment the instruction execution unit and/or the instruction memory system adjusts a width of the instruction word that determines a number of instructions from the instruction word that is processed in parallel, dependent on the detected range.

Abstract: A program of instruction words is executed with a VLIW data processing apparatus. The apparatus comprises a plurality of functional units capable of executing a plurality of instructions from each instruction word in parallel. The instructions from each of at least some of the instruction words are fetched from respective memory units in parallel, addressed with an instruction address that is common for the functional units. Translation of the instruction address into a physical address can be modified for one or more particular ones of the memory units. Modification is controlled by modification update instructions in the program. Thus, it can be selected dependent on program execution which instructions from the memory units will be combined into the instruction word in response to the instruction address.

Abstract: A method of packing a variable number of bits from an input bit stream into an output bit stream, comprising the steps of: defining a maximum number n of bits which are to be packed into the output bit stream within a clock cycle, providing a validation bit stream which defines positions of those bits in said input bit stream as output bits which are to be selected for packing; selecting the output bits and adding only the output bits to said output bit stream.

Abstract: The invention relates to a method of controlling decoder drift for memory compression comprising the steps of: providing a decoded bit-stream output of a decoder (79) and a bit-stream input to an encoder (76) in a first pass of a coding loop, where said bit-stream input to said encoder (76) is based on said decoded bit-stream output of said decoder (79); determining a difference between said bit-stream input to said encoder (76) and said decoded bit-stream output of said decoder (79), where said difference is due to a compression of said decoded bit-stream output of said decoder (79) in said encoder (76) during said first coding loop; and correcting said decoded bit-stream output of said decoder (79) in dependence on said determined difference in a second pass of said coding loop.

Abstract: The electronic circuit contains dual edge triggered flip-flop, which loads data on both the rising edge and the falling edge of a clock signal. The clock signal is supplied by a clock supply circuit with an enable input and a source input for receiving a source signal. The clock supply circuit toggles the clock signal as from an earliest available edge of the source signal after the enable signal at the enable input switches to an active state, irrespective of a polarity of said earliest available edge.