Patents by Inventor Rafael Serrano-Gotarredona

Rafael Serrano-Gotarredona has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240055464
    Abstract: An X-ray radiation sensor device may include a direct X-ray conversion layer, a plurality of electrodes to provide an electric charge in response to an interaction of an X-ray photon within the direct X-ray conversion layer, a plurality of pixel sensor arrays, and at least one interposer. The direct X-ray conversion layer and the plurality of electrodes are disposed on the top surface of the interposer(s). The plurality of the pixel sensor arrays is disposed on the bottom surface of the interposer(s), and the interposer(s) is configured to electrically couple each of the pixel sensor arrays to a respective portion of the plurality of electrodes.
    Type: Application
    Filed: November 23, 2021
    Publication date: February 15, 2024
    Inventors: José Manuel GARCÍA GONZÁLEZ, Joel BERTOMEU MESTRE, Harald ETSCHMAIER, Rafael SERRANO GOTARREDONA
  • Patent number: 11680969
    Abstract: A capacitance to digital converter, CDC, has a first and a second reference terminal for receiving first and second reference voltages, a reference block comprising one or more reference charge stores and being coupled to the first and second reference terminals via a first switching block, a scaling block for providing at third and fourth reference terminals downscaled voltages from the first and second reference voltages depending on a scaling factor, first and second measurement terminals for connecting a capacitive sensor element, the first measurement terminal being coupled to the third and fourth reference terminals via a second switching block, and a processing block coupled to the reference block and to the second measurement terminal and being configured to determine a digital output signal based on a charge distribution between the sensor element and the reference block and based on the scaling factor, the output signal representing a capacitance value of the sensor element.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: June 20, 2023
    Assignee: ams AG
    Inventors: Rafael Serrano Gotarredona, José Manuel García González
  • Publication number: 20230175890
    Abstract: A spectrometer includes an emitter that is configured to emit electromagnetic radiation, a sample area that is arranged at an outer face of the spectrometer, a modulation unit including an electrochromic material, an optical filter, an optical detector, an integrated circuit that has a main plane of extension, and an optical path for electromagnetic radiation emitted by the emitter towards the optical detector via the sample area, the modulation unit and the optical filter, wherein the electrochromic material is electrically connected with the integrated circuit, and the modulation unit is configured to modulate electromagnetic radiation temporally. Furthermore, a method for detecting electromagnetic radiation is provided.
    Type: Application
    Filed: May 4, 2021
    Publication date: June 8, 2023
    Applicant: ams-OSRAM AG
    Inventors: Deborah MORECROFT, Fernando Jesus CASTANO SANCHEZ, Richard HOPPER, Sophie BOUAL, Gerhard EILMSTEINER, Rafael SERRANO GOTARREDONA, Jozef PULKO, Gerald MEINHARDT
  • Publication number: 20220034950
    Abstract: A capacitance to digital converter, CDC, has a first and a second reference terminal for receiving first and second reference voltages, a reference block comprising one or more reference charge stores and being coupled to the first and second reference terminals via a first switching block, a scaling block for providing at third and fourth reference terminals downscaled voltages from the first and second reference voltages depending on a scaling factor, first and second measurement terminals for connecting a capacitive sensor element, the first measurement terminal being coupled to the third and fourth reference terminals via a second switching block, and a processing block coupled to the reference block and to the second measurement terminal and being configured to determine a digital output signal based on a charge distribution between the sensor element and the reference block and based on the scaling factor, the output signal representing a capacitance value of the sensor element.
    Type: Application
    Filed: September 25, 2019
    Publication date: February 3, 2022
    Inventors: Rafael SERRANO GOTARREDONA, José Manuel GARCÍA GONZÁLEZ
  • Patent number: 11095262
    Abstract: A circuit arrangement comprises a first input node, a first output node, a sampling capacitor means and a first switching means being switchable between a first switching state and a second switching state. The first switching means is coupled to the sampling capacitor means, the first input node and the first output node in such a way that the sampling capacitor means is conductively connected to the first input node and disconnected from the first output node in the first switching state and the sampling capacitor means is disconnected from the first input node and conductively connected to the first output node in the second switching state. A first charge-storing element is coupled via a second switching means to the first input node in such a way that the charge-storing element is charged in the first switching state and discharged in the second switching state, thereby at least partly compensating current flow for charging the sampling capacitor means in the first switching state.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: August 17, 2021
    Assignee: AMS AG
    Inventors: Jose Manuel Garcia Gonzalez, Rafael Serrano Gotarredona
  • Patent number: 11031949
    Abstract: An analog-to-digital converter comprises a first integrator (40), a first converter input (19), a first reference voltage input (34), a capacitor array (68) comprising capacitor elements (171), and a rotation frequency control unit (37) providing a rotation signal (SRO) with at least two different values of a rotation frequency (fR). A first subset of capacitor elements (171) of the capacitor array (68) is coupled to the first converter input (19) and to an input side of the first integrator (40) in a first phase and is coupled to the first reference voltage input (34) and to the input side of the first integrator (40) in a second phase as a function of the rotation signal (SRO).
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: June 8, 2021
    Assignee: AMS AG
    Inventors: Jose Manuel García González, Rafael Serrano Gotarredona
  • Publication number: 20210143835
    Abstract: An analog-to-digital converter comprises a first integrator (40), a first converter input (19), a first reference voltage input (34), a capacitor array (68) comprising capacitor elements (171), and a rotation frequency control unit (37) providing a rotation signal (SRO) with at least two different values of a rotation frequency (fR). A first subset of capacitor elements (171) of the capacitor array (68) is coupled to the first converter input (19) and to an input side of the first integrator (40) in a first phase and is coupled to the first reference voltage input (34) and to the input side of the first integrator (40) in a second phase as a function of the rotation signal (SRO).
    Type: Application
    Filed: March 20, 2018
    Publication date: May 13, 2021
    Inventors: Jose Manuel Gonzalez, Rafael SERRANO GOTARREDONA
  • Publication number: 20200220510
    Abstract: A circuit arrangement comprises a first input node, a first output node, a sampling capacitor means and a first switching means being switchable between a first switching state and a second switching state. The first switching means is coupled to the sampling capacitor means, the first input node and the first output node in such a way that the sampling capacitor means is conductively connected to the first input node and disconnected from the first output node in the first switching state and the sampling capacitor means is disconnected from the first input node and conductively connected to the first output node in the second switching state. A first charge-storing element is coupled via a second switching means to the first input node in such a way that the charge-storing element is charged in the first switching state and discharged in the second switching state, thereby at least partly compensating current flow for charging the sampling capacitor means in the first switching state.
    Type: Application
    Filed: July 18, 2018
    Publication date: July 9, 2020
    Inventors: Jose Manuel GARCIA GONZALEZ, Rafael SERRANO GOTARREDONA
  • Patent number: 10338022
    Abstract: A sensor circuit for measuring a physical or chemical quantity comprises a capacitive sensor. A sense and a base electrode of the sensor form a capacitive element with a capacity depending on the quantity. A common electrode of the sensor forms a first and a second parasitic capacitance together with the sense and the base electrode, respectively. The sensor circuit is adapted to store a charge on the capacitive element and to read out the stored charge via the sense electrode. A buffer element is connected between the sense electrode and the common electrode and adapted to drive the common electrode at a voltage applied to the sense electrode.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: July 2, 2019
    Assignee: ams AG
    Inventors: José Manuel García González, Rafael Serrano Gotarredona
  • Publication number: 20180136158
    Abstract: A sensor circuit for measuring a physical or chemical quantity comprises a capacitive sensor. A sense and a base electrode of the sensor form a capacitive element with a capacity depending on the quantity. A common electrode of the sensor forms a first and a second parasitic capacitance together with the sense and the base electrode, respectively. The sensor circuit is adapted to store a charge on the capacitive element and to read out the stored charge via the sense electrode. A buffer element is connected between the sense electrode and the common electrode and adapted to drive the common electrode at a voltage applied to the sense electrode.
    Type: Application
    Filed: March 29, 2016
    Publication date: May 17, 2018
    Inventors: José Manuel GARCÍA GONZÁLEZ, Rafael SERRANO GOTARREDONA
  • Patent number: 9438261
    Abstract: A capacitance-to-digital converter (10) comprises a capacitor arrangement (30), a converter (1) that is coupled on its input side to the capacitor arrangement (30) and a calibration unit (13) that is coupled on its input side to the converter (1). The capacitor arrangement (30) comprises an input capacitor (16).
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: September 6, 2016
    Assignee: AMS AG
    Inventors: Jose Manuel Garcia Gonzalez, Joel Bertomeu Mestre, Rafael Serrano Gotarredona
  • Publication number: 20150295587
    Abstract: A capacitance-to-digital converter (10) comprises a capacitor arrangement (30), a converter (1) that is coupled on its input side to the capacitor arrangement (30) and a calibration unit (13) that is coupled on its input side to the converter (1). The capacitor arrangement (30) comprises an input capacitor (16).
    Type: Application
    Filed: April 9, 2015
    Publication date: October 15, 2015
    Inventors: Jose Manuel GARCIA GONZALEZ, Joel BERTOMEU MESTRE, Rafael SERRANO GOTARREDONA
  • Patent number: 9077365
    Abstract: An integrated circuit includes a detector having a detecting device that detects a proximity condition and develops a parameter of electric power related thereto and a parameter measuring device coupled to the detecting device. The parameter measuring device comprises a parameter detector, and an analog-to digital converter (ADC) coupled to the parameter detector and operative in one of a plurality of operational ranges to develop a digital representation of the parameter. The parameter measuring device further includes a range selector coupled between the ADC and the parameter detector that is operative to cause the parameter detector to develop an output signal magnitude representative of the parameter of electric power wherein the output signal magnitude is within one of the operational ranges of the ADC. The detector may be used in a control for a spray device to detect motion.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: July 7, 2015
    Assignee: S.C. Johnson & Son, Inc.
    Inventors: Gene Sipinski, Joel Bertomeu, Juan Gavillero, Rafael Serrano-Gotarredona
  • Publication number: 20120091219
    Abstract: An integrated circuit includes a detector having a detecting device that detects a proximity condition and develops a parameter of electric power related thereto and a parameter measuring device coupled to the detecting device. The parameter measuring device comprises a parameter detector, and an analog-to digital converter (ADC) coupled to the parameter detector and operative in one of a plurality of operational ranges to develop a digital representation of the parameter. The parameter measuring device further includes a range selector coupled between the ADC and the parameter detector that is operative to cause the parameter detector to develop an output signal magnitude representative of the parameter of electric power wherein the output signal magnitude is within one of the operational ranges of the ADC. The detector may be used in a control for a spray device to detect motion.
    Type: Application
    Filed: October 15, 2010
    Publication date: April 19, 2012
    Inventors: Gene Sipinski, Joel Bertomeu, Juan Gavillero, Rafael Serrano-Gotarredona