Abstract: A monitoring system includes: a sensor configured to generate a sensor signal based on a measured property; a controller configured to communicate with the sensor; and a communication channel electrically coupled to the sensor and the controller for carrying electrical communications therebetween. The sensor includes a transmitter configured to transmit an electrical signal on the communication channel to the controller. The controller includes a processing circuit configured to receive the electrical signal, measure an actual signal function response of the electrical signal, correlate the actual signal function response with a reference signal function response to generate a correlation value, compare the correlation value and a correlation threshold to produce a comparison result, and detect a fault based on the comparison result indicating that the correlation value satisfies the correlation threshold.

Abstract: A method for configuring a storage circuit, including: writing data via an input line into the storage circuit by a software write access; writing a bit-wise inverted form of the data via the input line into the storage circuit by a subsequent software write access; and generating an error signal if a comparison based on the written data and the written bit-wise inverted form of the data indicates a storage circuit configuration error, wherein the storage circuit permits hardware read access and lacks software read access.

Abstract: In some examples, this disclosure describes a method of operating a circuit. The method may comprise performing a circuit function under normal operating conditions, wherein performing the circuit function under the normal operating conditions includes performing at least a portion of the circuit functions via a characteristic circuit, performing at least the portion of the circuit function under enhanced stress conditions via a characteristic circuit replica, and predicting a potential future problem with the circuit function under the normal conditions based on an evaluation of operation of the characteristic circuit relative to operation of the characteristic circuit replica.

Abstract: In some examples, a method of operating a circuit may comprise performing a circuit function under normal conditions, performing the circuit function under aggravated conditions, predicting a potential future problem with the circuit function under the normal conditions based on an output of the circuit function under the aggravated conditions, and outputting a predictive alert based on predicting the potential future problem.

Abstract: In some examples, a method comprises performing a circuit function via a circuit; and estimating a remaining life of the circuit. Moreover, estimating the remaining life of the circuit may include measuring one or more circuit parameters over a period of time during operation of the circuit, and estimating the remaining life of the circuit based on the one or more measured circuit parameters over the period of time during operation of the circuit.

Abstract: In some examples, a method of operating a circuit is described. The method may include performing a circuit function and estimating a probability of failure of the circuit based on one or more stress origination metrics, one or more stress victim events, and one or more initial state conditions.

Abstract: In some examples, a circuit comprises a function unit configured to perform a circuit function, and one or more in situ monitors configured to measure internal data associated with the circuit. The circuit may further comprise a memory configured to store one or more limit values associated with the one or more in situ monitors, and a lifetime model unit configured to determine whether the circuit has reached an end-of-life threshold based on the measured internal data from the one or more in situ monitors and the limit values.

Abstract: In some examples, this disclosure describes a method of operating a circuit. The method may comprise performing a circuit function under normal operating conditions, wherein performing the circuit function under the normal operating conditions includes performing at least a portion of the circuit functions via a characteristic circuit, performing at least the portion of the circuit function under enhanced stress conditions via a characteristic circuit replica, and predicting a potential future problem with the circuit function under the normal conditions based on an evaluation of operation of the characteristic circuit relative to operation of the characteristic circuit replica.

Abstract: In some examples, a method of operating a circuit may comprise performing a circuit function under normal conditions, performing the circuit function under aggravated conditions, predicting a potential future problem with the circuit function under the normal conditions based on an output of the circuit function under the aggravated conditions, and outputting a predictive alert based on predicting the potential future problem.

Abstract: An error diagnosis circuit includes a signal input for connection to a communication interface, configured to receive a first instruction and a second instruction for a device. A circuit is configured to compare the first instruction and the second instruction and to output an error signal if the first instruction and the second instruction differ from one another.

Abstract: In some examples, a circuit may be configured to perform a method that includes performing a circuit function via a circuit function unit of a circuit, receiving sensor data from one or more sensors associated with the circuit function unit, and estimating a remaining life of the circuit based on an accelerated reliability model and the sensor data, wherein the sensor data comprises input to the accelerated reliability model. The circuit itself may include a dedicated circuit unit that estimates the remaining life of the circuit based on an accelerated reliability model and the sensor data, and the circuit may output one or more predictive alerts or predictive faults when the remaining life is below a threshold, which may prompt the system for predictive maintenance on the circuit.

Abstract: A method for operating a microcontroller, which includes a processor and a peripheral circuit on a common chip, the method including initiating a process in the peripheral circuit, in the peripheral circuit generating recovery data, executing the process, checking whether the process has been executed successfully and, in the event that the check reveals that the process has not been executed successfully, generating recovered data from the recovery data, and executing the process again.

Abstract: A method for configuring a storage circuit, including: writing data via an input line into the storage circuit by a software write access; writing a bit-wise inverted form of the data via the input line into the storage circuit by a subsequent software write access; and generating an error signal if a comparison based on the written data and the written bit-wise inverted form of the data indicates a storage circuit configuration error, wherein the storage circuit permits hardware read access and lacks software read access.

Abstract: A method for operating a microcontroller, which includes a processor and a peripheral circuit on a common chip, the method including initiating a process in the peripheral circuit, in the peripheral circuit generating recovery data, executing the process, checking whether the process has been executed successfully and, in the event that the check reveals that the process has not been executed successfully, generating recovered data from the recovery data, and executing the process again.

Abstract: A microcontroller system includes a processing unit, a first peripheral having a first set of registers, and an assurance module. The first peripheral is configured to receive a first reset signal that resets the first set of registers to a first actual reset value, which is expected to be a first expected value. The assurance module is configured to calculate a first signature value, which is based on the first actual reset value, in response to the first reset signal. The processing unit is configured to perform a first comparison between the calculated first signature value and a pre-determined first signature value to determine whether the microcontroller system is in a trusted safety state. The first comparison is performed in response to the first reset signal, and the pre-determined first signature value is based on the first expected value.

Abstract: A microcontroller system includes a processing unit, a first peripheral having a first set of registers, and an assurance module. The first peripheral is configured to receive a first reset signal that resets the first set of registers to a first actual reset value, which is expected to be a first expected value. The assurance module is configured to calculate a first signature value, which is based on the first actual reset value, in response to the first reset signal. The processing unit is configured to perform a first comparison between the calculated first signature value and a pre-determined first signature value to determine whether the microcontroller system is in a trusted safety state. The first comparison is performed in response to the first reset signal, and the pre-determined first signature value is based on the first expected value.

Abstract: The present disclosure relates to a method of advanced motor control that reduces the resource demands (e.g., run-time) used to meet safety requirements by running a reduced portion of feedback control loop processes twice. In some embodiments, the method performs a plurality of processes within a feedback control loop of a motor control process configured to control operation of a motor. Performance of a first portion of the plurality of processes, which is less than the plurality of processes, is repeated within the feedback control loop. Performance of a second portion of the plurality of processes is not repeated within the feedback control loop. By repeating performance of first portion of the plurality of processes that is less than the plurality of processes, the method is able to improve performance of a motor by reducing run-time of the motor control process.

Abstract: The present disclosure relates to a method of advanced motor control that reduces the resource demands (e.g., run-time) used to meet safety requirements by running a reduced portion of feedback control loop processes twice. In some embodiments, the method performs a plurality of processes within a feedback control loop of a motor control process configured to control operation of a motor. Performance of a first portion of the plurality of processes, which is less than the plurality of processes, is repeated within the feedback control loop. Performance of a second portion of the plurality of processes is not repeated within the feedback control loop. By repeating performance of first portion of the plurality of processes that is less than the plurality of processes, the method is able to improve performance of a motor by reducing run-time of the motor control process.

Abstract: A method is disclosed for transmitting user data, wherein a first codeword is initially calculated using a transmit-side time value. The user data are then transmitted together with the first codeword to a receiver. The method continues with the calculation of a second codeword using a receive-side time value. If the first codeword and the calculated second codeword do not match one another, the user data are marked in the receiver.

Abstract: Some embodiments of the invention relate to a single processor configured to comprise configurable hardware extensions, disposed within a data path configured to selectively provide either encoded data or original data, that allow for two modes of operation. In a high performance mode, the hardware extensions allow for increased processing bandwidth by using the hardware extensions for processing extended data (i.e., additional original data). In a safety integrity mode the hardware extensions allow for parallel processing of encoded data concurrent with the processor executing a SBST by processing a self-test program and self-test data. Therefore, the single channel processor provides a single core system that can selectively achieve either high safety integrity levels (e.g., SIL3) for safety relevant applications or high performance for non-safety relevant applications.