Patents by Inventor Rafal SZTEJNA

Rafal SZTEJNA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220201061
    Abstract: Examples described herein relate to a packet processing device that includes circuitry to form one or more packets with raw media data for transmission to a sender based on a Real-time Transport Protocol (RTP). In some examples, the circuitry is to form one or more packets with raw pixel media in a manner consistent with Society of Motion Picture and Television Engineers (SMPTE) 2110 (2018). In some examples, the raw media data comprises one or more of: raw video and/or raw audio data.
    Type: Application
    Filed: March 8, 2022
    Publication date: June 23, 2022
    Inventors: Rafal SZTEJNA, Vipin VARGHESE
  • Publication number: 20220058062
    Abstract: Examples described herein relate to an including at least one processor and a system agent communicatively coupled to the at least one processor. In some examples, the at least one of the at least one processor, when operational, is configured to: execute an operating system (OS) to: receive a call to perform a kernel-level operation and adjust settings of system resources assigned to perform the kernel-level operation based on a class of service associated with the call.
    Type: Application
    Filed: November 7, 2021
    Publication date: February 24, 2022
    Inventors: Rafal SZTEJNA, Piotr WYSOCKI, Pawel ZAK, Przemyslaw PERYCZ, Szymon KONEFAL
  • Publication number: 20220027278
    Abstract: Examples include techniques for core-specific metrics collection. Examples include fetching metrics of a core of a multi-core processor from one or more registers responsive to scheduling of an event. The fetched metrics are pushed to a shared memory space of a memory that is accessible to a user-space application and accessible to other cores of the multi-core processor. The user-space application to access the shared memory space to aggregate core-specific metrics associated with at least the core of the multi-core processor and then publish the aggregated core-specific metrics.
    Type: Application
    Filed: October 6, 2021
    Publication date: January 27, 2022
    Inventors: Piotr WYSOCKI, Francesc GUIM BERNAT, John J. BROWNE, Pawel ZAK, Rafal SZTEJNA, Przemyslaw PERYCZ, Timothy VERRALL, Szymon KONEFAL