Abstract: In an embodiment, a method for re-programming memory is disclosed. In the embodiment, the method involves selecting a memory page based on version information and re-programming the selected memory page using cyclic redundancy check (CRC) data for the memory page.

Abstract: In an embodiment, a method for re-programming memory is disclosed. In the embodiment, the method involves selecting a memory page based on version information and re-programming the selected memory page using cyclic redundancy check (CRC) data for the memory page.

Abstract: A complex integrated circuit comprises at least a plurality of modules coupled together through at least a system channel. The circuit further comprises a plurality of input/output devices for interfacing the circuit with structures outside the circuit. The plurality of input/output devices comprise at least a first circuit portion implemented as a module coupled to the remaining modules of the circuit by the first channel system (BUS1).

Abstract: A multiplier circuit multiplies together both natural and two's complement binary numbers, which it receives in the form of electric signals having predetermined logic values, that are applied to input terminals of logic gating circuits. The logic gating circuits provide partial products of the bits of the two binary factors, and a combinatorial network provides the final sum of the partial products. The partial multiplications that include at least one of the more significant bits of the operands are performed by logic gating circuits which can be enabled to also carry out a two's complement partial multiplication. The multiplier circuit further includes additional logic gating circuits which supply the combinatorial network with additive constants with predetermined logic values unrelated to the factors.

Abstract: A method for reducing the number of bits needed to represent constant values in a data processing device. A group of constant values is defined by selecting them as a function of their statistical frequency of use. Each constant value of this group in the instructions is represented by means of a shorter coded operand field and a current instruction is loaded from a bus in an instruction register. A corresponding operand field is derived from the coded operand field of the current instruction by expansion means, and a bus and an output of the expansion means are selectively connected as input to an arithmetic logic unit.

Abstract: A multiplier circuit which multiplies together both natural and two's complement binary numbers, which it receives in the form of electric signals having predetermined logic values, that are applied to input terminals of logic gating circuits. The logic gating circuits provide partial products of the bits of the two binary numbers, and a combinatorial network provides the final sum of the partial products. The partial products that include at least one of the more significant bits of either of the operands are performed by logic gating circuits which can be enabled to complement the partial product. The multiplier circuit further includes additional logic gating circuits which supply the combinatorial network with additive constants with predetermined logic values.

Abstract: An integrated device with electrically programmable and erasable memory cells, including one time programmable (OTP) read-only memory cells. A matrix of user memory cells is added at least one row of OTP cells sharing the column selection lines with the other cells. Similarly to the other cells, these have a selection terminal connected to a row selection line. The source terminals of such OTP cells in the row are connected to the device ground through a common selection transistor which is driven from the same row selection line.

Abstract: A multiplier circuit which multiplies together both natural and two's complement binary numbers, which it receives in the form of electric signals having predetermined logic values, that are applied to input terminals of logic gating circuits. The logic gating circuits provide partial products of the bits of the two binary numbers, and a combinatorial network provides the final sum of the partial products. The partial products that include at least one of the more significant bits of either of the operands are performed by logic gating circuits which can be enabled to complement the partial product. The multiplier circuit further includes additional logic gating circuits which supply the combinatorial network with additive constants with predetermined logic values.