Patents by Inventor Raffaele Solimene

Raffaele Solimene has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6509768
    Abstract: A power-on reset circuit connected to a supply line feeding a supply voltage, the circuit including an output terminal supplying a power-on reset signal; a divider connected between the supply line (36) and ground and having an intermediate node supplying a division voltage correlated to the supply voltage; an inverter having an input connected to the intermediate node and an output connected to the output terminal and supplying a reset logic signal; and a deactivation branch coupled to the supply line and the intermediate node. The deactivation branch preventing switching of the power-on reset signal on the output terminal when the supply voltage is higher than a deactivation voltage.
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: January 21, 2003
    Assignee: STMicroelectronics S.r.L.
    Inventors: Salvatore Polizzi, Raffaele Solimene
  • Patent number: 6489807
    Abstract: A method is for driving an output buffer for outputting a datum of a certain voltage level with a certain slew-rate as a function of an input datum and a first enabling signal. The first enabling signal commands the buffer to a normal functioning state or to a high impedance state. The output buffer has an output stage controlled at least by a pull-up driving circuit and a pull-down driving circuit, and an enabling circuit input with the input datum and a second enabling signal and generating control signals. The control signals may be in phase or in phase opposition depending on whether the second enabling signal is active or disabled, and they are input into the respective driving circuits.
    Type: Grant
    Filed: August 8, 2001
    Date of Patent: December 3, 2002
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giovanni Genna, Raffaele Solimene
  • Patent number: 6442072
    Abstract: The selection/deselection circuit is for non-volatile memory word lines having a decoding line connected between a supply voltage and ground, and including a series of decoding transistors of the same conductivity controlled by respective selection signals and at least a load transistor whose conductivity is opposite to the conductivity of the decoding transistors in series with the series of transistors and biased by a control voltage. The load transistor produces an activating or deactivating voltage of a memory word line, and a circuit for controlling the load transistor is provided. Such an auxiliary control circuit includes a sensing element in series with the decoding transistors and the load transistor for producing a sensing signal switching between a first value when only one memory line is actually selected and a second value when multiple memory word lines appear to be simultaneously selected.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: August 27, 2002
    Assignee: STMicroelectronics S.R.L.
    Inventor: Raffaele Solimene
  • Publication number: 20020105356
    Abstract: A method is for driving an output buffer for outputting a datum of a certain voltage level with a certain slew-rate as a function of an input datum and a first enabling signal. The first enabling signal commands the buffer to a normal functioning state or to a high impedance state. The output buffer has an output stage controlled at least by a pull-up driving circuit and a pull-down driving circuit, and an enabling circuit input with the input datum and a second enabling signal and generating control signals. The control signals may be in phase or in phase opposition depending on whether the second enabling signal is active or disabled, and they are input into the respective driving circuits.
    Type: Application
    Filed: August 8, 2001
    Publication date: August 8, 2002
    Applicant: STMicroelectronics S.r.l.
    Inventors: Giovanni Genna, Raffaele Solimene
  • Publication number: 20010024131
    Abstract: The selection/deselection circuit is for non-volatile memory word lines having a decoding line connected between a supply voltage and ground, and including a series of decoding transistors of the same conductivity controlled by respective selection signals and at least a load transistor whose conductivity is opposite to the conductivity of the decoding transistors in series with the series of transistors and biased by a control voltage. The load transistor produces an activating or deactivating voltage of a memory word line, and a circuit for controlling the load transistor is provided. Such an auxiliary control circuit includes a sensing element in series with the decoding transistors and the load transistor for producing a sensing signal switching between a first value when only one memory line is actually selected and a second value when multiple memory word lines appear to be simultaneously selected. Also, an inverter receives the sensing signal and outputs a first signal.
    Type: Application
    Filed: December 21, 2000
    Publication date: September 27, 2001
    Applicant: STMicroelectronics S.r.I
    Inventor: Raffaele Solimene
  • Publication number: 20010019281
    Abstract: A power-on reset circuit connected to a supply line feeding a supply voltage, the circuit including an output terminal supplying a power-on reset signal; a divider connected between the supply line (36) and ground and having an intermediate node supplying a division voltage correlated to the supply voltage; an inverter having an input connected to the intermediate node and an output connected to the output terminal and supplying a reset logic signal; and a deactivation branch coupled to the supply line and the intermediate node. The deactivation branch preventing switching of the power-on reset signal on the output terminal when the supply voltage is higher than a deactivation voltage.
    Type: Application
    Filed: January 25, 2001
    Publication date: September 6, 2001
    Inventors: Salvatore Polizzi, Raffaele Solimene
  • Patent number: 6240002
    Abstract: A content addressable memory (CAM) protection circuit includes a memory cell having a read terminal for reading contents of the memory cell; a pass transistor coupled to the read terminal; and a latch having a first inverter with an input terminal and an output terminal coupled to the read terminal by the pass transistor and a second inverter with input and output terminals respectively coupled to the output and input terminals of the first inverter. The first inverter includes a pull-down transistor coupled between the output terminal of the first inverter and a first voltage reference and having a control terminal coupled to the input terminal of the latch and a pull-up transistor coupled between the output terminal of the first inverter and a second voltage reference and having a control terminal coupled to the input terminal of the latch.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: May 29, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Salvatore Polizzi, Raffaele Solimene