Patents by Inventor Raffi M. Garabedian

Raffi M. Garabedian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240372371
    Abstract: A DC power output system may achieve variable output power by paring a variable inverter with a rectifier.
    Type: Application
    Filed: December 8, 2022
    Publication date: November 7, 2024
    Inventor: Raffi M. GARABEDIAN
  • Publication number: 20240247386
    Abstract: The following disclosure relates to catalyst compositions for electrochemical cells and their methods of making. In one example, the method includes providing a supporting substrate and depositing an active catalyst composition onto a surface of the supporting substrate via atomic layer deposition (AID). A catalyst composition includes a conductive substrate and an active catalyst deposited on a surface of the conductive substrate via atomic layer deposition.
    Type: Application
    Filed: December 13, 2022
    Publication date: July 25, 2024
    Inventors: Raffi M. GARABEDIAN, Timothy J. KUCHARSKI
  • Patent number: 6211558
    Abstract: A surface micro-machined sensor uses a pedestal in a cavity to support a flexible structure and reduce the span of the flexible structure. The reduced span per sense area allows larger sensor areas without permitting forces to permanently deform the flexible structure or cause the structure to touch an opposite wall of the cavity. The flexible structure bonded to the pedestal and an elevated region surrounding the pedestal defines a cavity between the flexible membrane and a lower plane region. Active regions can be formed in the lower plane region for capacitors or transistors. A pedestal can be of various shapes including a circular, ovoid, rectangular or polygonal shape. The lower plane region can be of various shapes including a ring or donut shape, ovoid, rectangular or polygonal shape with an inner dimension corresponding to the outer dimension of the pedestal. The elevated region can be of various shapes with an inner dimension corresponding to the outer dimension of the lower plane region.
    Type: Grant
    Filed: July 18, 1997
    Date of Patent: April 3, 2001
    Assignee: Kavlico Corporation
    Inventors: M. Salleh Ismail, Raffi M. Garabedian
  • Patent number: 5929498
    Abstract: A semiconductor device has a flexible structure bonded to a semiconductor substructure to form a cavity. The flexible structure is bonded over a conducting feed-through without the feed-through interfering with a hermetic seal formed by bonding. One embodiment of the device includes depressions that contain edges of a diffused feed-through so that imperfections at the edge of the diffusion do not interfere with bonding. The flexible structure is bonded to elevated areas thus hiding the imperfections. In one embodiment, a first elevated region is surrounded by a second elevated region, and diffusion for the feed-through extends from an active region in the cavity across the first elevated region with edges of the diffusion being between the first and second elevated regions. The flexible structure can thus bond to the first and second elevated regions without interference from the edge of the diffused feed-through.
    Type: Grant
    Filed: March 17, 1998
    Date of Patent: July 27, 1999
    Assignee: Kavlico Corporation
    Inventors: M. Salleh Ismail, Raffi M. Garabedian, Max E. Nielsen, Gary J. Pashby, Jeffrey K. K. Wong
  • Patent number: 5923952
    Abstract: A semiconductor device has a flexible structure bonded to a semiconductor substructure to form a cavity. The flexible structure is bonded over a conducting feed-through without the feed-through interfering with a hermetic seal formed by bonding. One embodiment of the device includes depressions that contain edges of a diffused feed-through so that imperfections at the edge of the diffusion do not interfere with bonding. The flexible structure is bonded to elevated areas thus hiding the imperfections. In one embodiment, a first elevated region is surrounded by a second elevated region, and diffusion for the feed-through extends from an active region in the cavity across the first elevated region with edges of the diffusion being between the first and second elevated regions. The flexible structure can thus bond to the first and second elevated regions without interference from the edge of the diffused feed-through.
    Type: Grant
    Filed: July 18, 1997
    Date of Patent: July 13, 1999
    Assignee: Kavlico Corporation
    Inventors: M. Salleh Ismail, Raffi M. Garabedian, Max E. Nielsen, Gary J. Pashby, Jeffrey K. K. Wong
  • Patent number: 5578843
    Abstract: Fabrication of semiconductor devices with movable structures includes local oxidation of a wafer and oxide removal to form a depression in an elevated bonding surface. A second wafer is fusion bonded to the elevated bonding surface and shaped to form a flexible membrane. An alternative fabrication technique forms a spacer having a depression on a first wafer and active regions on a second wafer, and fusion bonds the wafers together with the depression over the active regions. Devices formed are integrable with standard MOS devices and include FETs, capacitors, and sensors with movable membranes. An FET sensor has gate and drain coupled together and a drain-source voltage which depends on the gate's deflection. Selected operating current, channel length, and channel width provide a drain-source voltage linearly related to gate deflection.
    Type: Grant
    Filed: October 6, 1994
    Date of Patent: November 26, 1996
    Assignee: Kavlico Corporation
    Inventors: Raffi M. Garabedian, M. Salleh Ismail, Gary J. Pashby
  • Patent number: 5576251
    Abstract: Fabrication of semiconductor devices with movable structures includes local oxidation of a wafer and oxide removal to form a depression in an elevated bonding surface. A second wafer is fusion bonded to the elevated bonding surface and shaped to form a flexible membrane. An alternative fabrication technique forms a spacer having a depression on a first wafer and active regions on a second wafer, and fusion bonds the wafers together with the depression over the active regions. Devices formed are integrable with standard MOS devices and include FETs, capacitors, and sensors with movable membranes. An FET sensor has gate and drain coupled together and a drain-source voltage which depends on the gate's deflection. Selected operating current, channel length, and channel width provide a drain-source voltage linearly related to gate deflection.
    Type: Grant
    Filed: February 22, 1995
    Date of Patent: November 19, 1996
    Assignee: Kavlico Corp.
    Inventors: Raffi M. Garabedian, M. Salleh Ismail, Gary J. Pashby, Jeffrey K. K. Wong