Abstract: Various approaches for computationally generating a protocol for treatment of one or more target BBB regions within a tissue region of interest using a source of focused ultrasound include specifying (i) settings of sonication parameters for applying one or more sequence of sonications to the target BBB region using the source of focused ultrasound and (ii) a characteristic of microbubbles selected to be administered into the target BBB region; electronically simulating treatment in accordance with the protocol at least in part by computationally executing the sequence(s) of sonications and computationally administering the microbubbles having the characteristic; and computationally predicting a tissue disruption effect of the target BBB region resulting from the treatment.

Abstract: Systems and methods for applying ultrasound sonication to temporarily disrupt a patient's blood-brain barrier (BBB) include storing threshold values of an acoustic response level, an acoustic response dose and a tissue response dose associated with a target BBB region and its surrounding regions based on anatomical characteristics thereof; causing the ultrasound transducer to transmit one or more pulses/waves; measuring the acoustic response level, the acoustic response dose, and/or the tissue response dose associated with the target BBB region and/or its surrounding regions; comparing the measurement with a corresponding stored threshold value; and operating the transducer based at least in part on the comparison.

Abstract: Processes and systems (300) for reducing pessimism in cross talk noise aware static timing analysis and thus resulting false path failures use either or both of effective delta delay noise (307) and path based delay noise (311) analysis. Effective delta delay determines an impact (312, 314, 316) on victim timing of an action by aggressors that occur during a region (209, 319, 321) where victim and aggressor timing windows overlap and determines an effective delta delay 317 corresponding to any portion 316 of the impact on victim timing that extends beyond the victim timing window. The effective delta delay is used to adjust the victim timing window. Path based delta delay determines an uncertainty (627, 637) in a switching time corresponding to a particular path for a victim resulting from an action (switching) by aggressors that occurs at the switching time 607, 613, i.e. during a switching time window (a2 to a2+u1) (613, 625) when uncertainty is included.

Abstract: Processes and systems (300) for reducing pessimism in cross talk noise aware static timing analysis and thus resulting false path failures use either or both of effective delta delay noise (307) and path based delay noise (311) analysis. Effective delta delay determines an impact (312, 314, 316) on victim timing of an action by aggressors that occur during a region (209, 319, 321) where victim and aggressor timing windows overlap and determines an effective delta delay 317 corresponding to any portion 316 of the impact on victim timing that extends beyond the victim timing window. The effective delta delay is used to adjust the victim timing window. Path based delta delay determines an uncertainty (627, 637) in a switching time corresponding to a particular path for a victim resulting from an action (switching) by aggressors that occurs at the switching time 607, 613, i.e. during a switching time window (a2 to a2+u1) (613, 625) when uncertainty is included.

Abstract: A solution to perform cross coupling delay characterization for integrated circuits and other microprocessor applications. The invention properly models the integrated circuit in various configurations at various times to accommodate the non-linearities associated with driver circuitry and the undesirable capacitive coupling between nets within the integrated circuit, specifically those that are located within close proximity to one another and that generate deleterious effects of the transitions of the drivers from low to high, and from high to low. The invention provides for a computationally efficient solution to perform the delay characterization of the speeding up and slowing down of individual transition operations within the microprocessor.

Abstract: Method for generating a set of switching vectors where each vector S1-Si causes the output X to transition in the predetermined way provided that the input A transitions in the selected way. This method may be used for any electrical circuit cluster, including the simple one illustrated in FIG. 3. This method handles any number of side inputs, gate clusters which have feedback within the gate cluster, and gate clusters which have internal nodes that may be in a third state other than a logic level one or a logic level zero (e.g. a high impedance state).