Abstract: Various semiconductor chip devices and methods of assembling the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a frame to a surface of a substrate. The surface of the substrate is adapted to hold a first semiconductor chip that includes an upper surface. The frame includes an internal wall that is adapted to engage plural sidewalls of the first semiconductor chip. A portion of the internal wall and at least a portion of the upper surface are adapted to define an internal space.

Abstract: Methods and apparatus for clamping a first circuit board against a member are provided where the first circuit board has a first side and a second side opposite the first side. The method includes engaging an elastomeric member of a clamping member with the first side of the first circuit board to compliantly bear against the first side of the first circuit board whereby the second side of the circuit board is clamped against the member.

Abstract: A system and method are provided to measure a total force applied by a device to a device under test on a circuit board.

Abstract: Systems and methods of measuring force on dies and substrates are provided. In one system, a force measurement die is substituted for a die to be tested on a substrate.

Abstract: A burn-in board and a method for thermally testing the burn-in board determines if the burn-in board is defective. The burn-in board includes components on a front side of the burn-in board and thermal tape on the back side of the burn-in board. Power and ground are supplied to the burn-in board and the thermal tape changes color indicating a hot spot if the burn-in board contains one or more problem areas.

Abstract: A multi-layered pin grid array interposer used in a test socket for testing and converting a package having a non-pin grid array footprint to a pin grid array footprint. The multi-layered pin grid array interposer test socket includes a multi-layered pin grid array interposer, a semiconductor device mounted on a package having a non-grid array footprint and a fastener. The multi-layered pin grid array interposer includes a top signal layer having bonding pads on an upper surface, a bottom signal layer having a pin grid array footprint on a bottom surface, at least one power layer between ground layers, the ground layers being between the top signal layer and bottom signal layer, and a links for connecting the plurality of bonding pads to the pins of the pin grid array footprint. The fastener presses the package against the multi-layered pin grid array interposer connecting the leads of the package with the bonding pads.

Abstract: A system level test socket for testing semiconductor packages having non-pin grid array footprints. The test socket having solder pads positioned on the test socket to form electrical connections with corresponding leads on the bottom of the semiconductor package. The test socket has internal connections connecting each solder pad with a corresponding connection on the bottom of the test socket. The test socket is mounted on a burn-in board, thus allowing a semiconductor package having a non-pin grid array footprint to be tested without requiring an interposer for converting the non-pin grid array footprint of the semiconductor package. In addition, the test socket includes guide posts which align with guide slots on a hydraulic cylinder. The hydraulic cylinder compresses the semiconductor package to the test socket thereby ensuring solid connections between the semiconductor package and test socket.

Abstract: A system level test socket for testing semiconductor packages having non-pin grid array footprints. The test socket having solder pads positioned on the test socket to form electrical connections with corresponding leads on the bottom of the semiconductor package. The test socket has internal connections connecting each solder pad with a corresponding connection on the bottom of the test socket. The test socket is mounted on a burn-in board, thus allowing a semiconductor package having a non-pin grid array footprint to be tested without requiring an interposer for converting the non-pin grid array footprint of the semiconductor package. In addition, the test socket includes guide posts which align with guide slots on a hydraulic cylinder. The hydraulic cylinder compresses the semiconductor package to the test socket thereby ensuring solid connections between the semiconductor package and test socket.

Abstract: There is provided an improved stacking scheme for micro-BGA packages so as to provide a high density integrated circuit package. The integrated circuit package assembly (300) includes a sheet-like interposer (312) which is formed of a main portion (312a) and an extension (312b) extending outwardly from the main portion. A plurality of lands (326) are disposed on the surface of the interposer extension. A plurality of masses (314) of electrically conductive bonding material of each of a plurality of packages overlie the lands on the interposer extension of the next lower package and are electrically connected thereto when the plurality of packages are stacked one atop the other.