Patents by Inventor Raghava Rao V. Denduluri

Raghava Rao V. Denduluri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hybrid pulse/two-stage data latch
    Patent number: 11870442
    Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: January 9, 2024
    Assignee: Apple Inc.
    Inventors: Vivekanandan Venugopal, Raghava Rao V. Denduluri, Ajay Bhatia, Suparn Vats, Suresh Balasubramanian, Gopinath Venkatesh, Teng Wang
  • Hybrid Pulse/Two-Stage Data Latch
    Publication number: 20220345117
    Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
    Type: Application
    Filed: July 12, 2022
    Publication date: October 27, 2022
    Inventors: Vivekanandan Venugopal, Raghava Rao V. Denduluri, Ajay Bhatia, Suparn Vats, Suresh Balasubramanian, Gopinath Venkatesh, Teng Wang
  • Hybrid pulse/two-stage data latch
    Patent number: 11418173
    Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: August 16, 2022
    Assignee: Apple Inc.
    Inventors: Vivekanandan Venugopal, Raghava Rao V. Denduluri, Ajay Bhatia, Suparn Vats, Suresh Balasubramanian, Gopinath Venkatesh, Teng Wang
  • Hybrid Pulse/Two-Stage Data Latch
    Publication number: 20200373915
    Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Inventors: Vivekanandan Venugopal, Raghava Rao V. Denduluri, Ajay Bhatia, Suparn Vats, Suresh Balasubramanian, Gopinath Venkatesh, Teng Wang
  • Hybrid pulse/master-slave data latch
    Patent number: 10742201
    Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: August 11, 2020
    Assignee: Apple Inc.
    Inventors: Vivekanandan Venugopal, Raghava Rao V. Denduluri, Ajay Bhatia, Suparn Vats, Suresh Balasubramanian, Gopinath Venkatesh, Teng Wang
  • HYBRID PULSE/MASTER-SLAVE DATA LATCH
    Publication number: 20200106425
    Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
    Type: Application
    Filed: January 9, 2019
    Publication date: April 2, 2020
    Inventors: Vivekanandan Venugopal, Raghava Rao V. Denduluri, Ajay Bhatia, Suparn Vats, Suresh Balasubramanian, Gopinath Venkatesh, Teng Wang
  • Execution unit power management
    Patent number: 10037073
    Abstract: A processor includes an instruction issue circuit, and high-utilization and low-utilization execution unit circuits coupled to execute instructions received from the instruction issue unit. On average, utilization of the low-utilization execution unit circuit is lower than utilization of the high-utilization execution unit circuit. The processor also includes a retention circuit coupled to a different power domain than the low-utilization execution unit circuit, and a power management circuit.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: July 31, 2018
    Assignee: Apple Inc.
    Inventors: Edvin Catovic, Rajat Goel, Richard F. Russo, Matthew R. Johnson, Shingo Suzuki, Pradeep Kanapathipillai, Raghava Rao V. Denduluri, Pankaj Lnu