Abstract: Techniques for key encapsulation mechanism (KEM) and digital signature authentication (DSA) are described. In some examples, at least one reconfigurable butterfly execution circuit that is reconfigurable to execute modular arithmetic instructions for both key encapsulation mechanism (KEM) and digital signature authentication (DSA) using polynomial data is provided. In some examples, number theoretic transform (NTT) circuitry to perform NTT operations and inverse number theoretic transform (iNTT) circuitry to perform iNTT operations, wherein the NTT and iNTT circuitry have a decimation-in-time (DIT) configuration is also provided.

Abstract: An apparatus comprises a push-pull regulation loop (PPRL). The PPRL comprises a PMOS transistor, an NMOS transistor, and a first plurality of capacitors. The PPRL also comprises a control circuit coupled to the PMOS transistor, the NMOS transistor, and the first plurality of capacitors. The control circuit comprises a reference terminal and is to receive a randomized voltage reference signal via the reference terminal. The control circuit further adjusts a reset voltage available at the first plurality of capacitors based on the randomized voltage reference signal.

Abstract: Techniques for number theoretic transform (NTT) and inverse number theoretic transform (iNTT) are described. In some examples, an NTT circuit is to use a decimation-in-frequency (DIF) data flow and a plurality of Cooley-Tukey butterfly stages, wherein input data is in a normal order and output data from the NTT circuit is in a bit reversed order. In some examples, an iNTT circuit is to use a decimation-in-time (DIT) data flow and a plurality of Cooley-Tukey butterfly stages, wherein input data is in a normal order and output data from the NTT circuit is in a bit reversed order.

Abstract: An apparatus comprises a push-pull regulation loop (PPRL), an input terminal, an output terminal, and a plurality of flying capacitor (FC) circuits. The plurality of FC circuits comprises a corresponding plurality of capacitors. The PPRL comprises a PMOS transistor, an NMOS transistor, and a control circuit. The input terminal and the output terminal are coupled to a node of the PPRL via a rail. FC circuits of the plurality of FC circuits are coupled to each other. At least a first FC circuit of the plurality of FC circuits is coupled to the rail. A remaining subset of the plurality of FC circuits is coupled to the first FC circuit. An FC circuit of the plurality of FC circuits further comprises at least a first transistor switch and a second transistor switch coupled to a corresponding capacitor of the plurality of capacitors.

Abstract: Apparatus and method for an attack resistant hardware accelerator. For example, one embodiment comprises an attack-resistant masked HMAC-SHA-2 accelerator with: (a) multiplexer-based implementations of masked choose (Ch) logic and majority (Maj) logic with implicit masked-domain non-linear computations; (b) Secure Binary to arithmetic (BtoA) conversion logic integrated within a masked carry-save-adder gate; and (c) an area-efficient arithmetic-to-Binary (AtoB) mask conversion circuit using a secure masked sparse-tree adder.

Abstract: Techniques for fully homomorphic encryption are described. In some examples, a fully homomorphic encryption includes a butterfly compute circuitry to support a polynomial integer multiplication in response to an instance of a single instruction of a first type, wherein the instance of the single instruction is at least to include one or more fields for a register file address for a first source operand of the integer multiplication, one or more fields for a register file address for a second source operand of the integer multiplication, and one more fields for a register file address for a result of the integer multiplication, wherein the butterfly compute circuitry is to additionally support modular arithmetic operations.

Abstract: An apparatus comprises a push-pull regulation loop (PPRL), an input terminal, an output terminal, and a plurality of FC circuits. The PPRL comprises a PMOS transistor, an NMOS transistor, and a first plurality of capacitors. The input terminal and the output terminal are coupled to the PPRL via the first plurality of capacitors. The plurality of FC circuits includes a second plurality of capacitors. FC circuits of the plurality of FC circuits are coupled to each other and a rail between the input terminal and the output terminal. An FC circuit of the plurality of FC circuits comprises at least a first transistor switch and a second transistor switch coupled to a corresponding capacitor of the second plurality of capacitors.

Abstract: Embodiments herein relate to countermeasures for electromagnetic (EM) probing attacks of voltage regulators (VRs) for cryptographic circuits. In one aspect, the clamp strength of a VR such as a switched-capacitor VR is dynamically and randomly modulated. The VR can include switches for transferring charge, where a switch can include a number of sub-switches in parallel, and the number of active switches is randomly varied to randomize the EM emissions. In another aspect, a capacitor of a VR is formed in a metal wiring layer of an integrated circuit package such as a top metal layer, where the capacitor has inter-digitated electrodes which cancel out current flows to/from the electrodes to reduce EM emissions. In another aspect, a resonant VR includes circuitry to detect changes in current or voltage which correlates with a change in its resonant frequency due to EM probing.

Abstract: A compute near memory (CNM) convolution accelerator enables a convolutional neural network (CNN) to use dedicated acceleration to achieve efficient in-place convolution operations with less impact on memory and energy consumption. A 2D convolution operation is reformulated as 1D row-wise convolution. The 1D row-wise convolution enables the CNM convolution accelerator to process input activations row-by-row, while using the weights one-by-one. Lightweight access circuits provide the ability to stream both weights and input rows as vectors to MAC units, which in turn enables modules of the CNM convolution accelerator to implement convolution for both [1×1] and chosen [n×n] sized filters.

Abstract: Techniques for static instruction decoupling for data movement and computer are described. In some examples, hardware support at least includes a plurality of instruction queues to store instructions, wherein each instruction queue of the plurality of instruction queues is dedicated to a separate thread; a local memory to store instructions and/or data for a first thread; a scratchpad memory, coupled to the local memory, to store instructions and/or data for a second thread; and execution resources, coupled to the scratchpad memory, to execute one or more mathematic and/or logical instructions for a third thread.

Abstract: In one embodiment, a method comprises: combining, in a first adder circuit of a cryptographic engine, a round key with masked plaintext to generate an additively masked input; converting, in a first converter of the cryptographic engine, the additively masked input to a multiplicatively masked input; and performing, in a substitution box circuit of the cryptographic engine, a non-linear inverse operation on the multiplicatively masked input when the multiplicatively masked input is non-zero, and performing the non-linear inverse operation on a random non-zero value when the multiplicatively masked input is zero. Other embodiments are described and claimed.

Abstract: An apparatus is described. The apparatus includes a long short term memory (LSTM) circuit having a multiply accumulate circuit (MAC). The MAC circuit has circuitry to rely on a stored product term rather than explicitly perform a multiplication operation to determine the product term if an accumulation of differences between consecutive, preceding input values has not reached a threshold.

Abstract: An on-die key generator includes a pseudo-random number generator (PRNG) and a sampler. The pseudo-random number generator generates integers modulo a power-of-two number, based on an initial seed. The sampler uniformly maps the integers generated by the random number generator (RNG) from the number space of 0?(2n?1) to the ciphertext modulus space of 0?(q?1) by randomly mapping the integers generated by the pseudo-random number generator that are greater than or equal to q to a value inside the range [0, q?1] using additional random bits.

Abstract: Compute circuitry to perform Fully Homomorphic Encryption (FHE) includes a memory system and a compute engine. The compute engine includes tiles organized in an array. The array of tiles in the compute engine provides compute elements to perform polynomial operations for polynomials. Synchronization support is provided by a Compute Engine Control Block (CCB) in the compute circuitry. The Compute Engine Control Block decomposes large data word loads and stores (with data spread across memory channels) into smaller requests for each memory channel. The Compute Engine Control Block uses completion signals received from each memory channel to assess the completion state of the large data word load/store. The Compute Engine Control Block to manage instruction dispatch across all tiles in the array of tiles and to ensure the tiles in the compute engine to operate in lockstep to enable synchronization free communication between the tiles.

Abstract: Examples include techniques for contention-free routing for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations routed through a parallel processing device. Examples include a tile array that includes a plurality of tiles arranged in a 2-dimensional mesh interconnect-based architecture. Each tile includes a plurality of compute elements configured to execute NTT or iNTT computations associated with a fully homomorphic encryption workload. Contention-free routing to include use of grouped or compressed source addresses to be used in routing tables maintained at tiles of the tile array.

Abstract: Examples include techniques for contention-free routing for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations routed through a parallel processing device. Examples include a tile array that includes a plurality of tiles arranged in a 2-dimensional mesh interconnect-based architecture. Each tile includes a plurality of compute elements configured to execute NTT or iNTT computations associated with a fully homomorphic encryption workload. Contention-free routing to include use of selective stalls and destination ports indicated in routing tables maintained at tiles of the tile array can facilitate NTT/iNTT computation throughput through the parallel processing device.

Abstract: An apparatus and method for attack-resistant encryption and decryption. For example, one embodiment of an apparatus comprises: execution circuitry to execute instructions and generate memory access requests including load requests to read data from memory and store requests to store data to memory; and cryptographic circuitry to perform a plurality of rounds of encryption or decryption to encrypt or decrypt the data, respectively, the cryptographic circuitry to perform one or more redundant rounds for a corresponding one or more of the plurality of rounds, the one or more redundant rounds to include spatial or temporal differences relative to the corresponding one or more rounds; the cryptographic circuitry to generate a fault upon detecting a mismatch between an output of a redundant round output and an output of a corresponding round.

Abstract: Efficient generation of uniform random numbers for FHE public key generation across varying prime numbers with different bit width is provided by configuring an xorshift linear feedback shift register (LFSR) based Random Number Generator (RNG) to optimal bit width while maintaining the uniformity properties. The prime value and corresponding xorshift RNG tap locations are used to configure the xorshift LFSR based RNG to generate the random numbers between [0, 2m] where m is configured to generate the next power of 2 corresponding to a selected prime q value. The configuration of the xorshift LFSR based RNG reduces the worst-case rejection rate from 100% to 50% across prime q values from 17 bits to 32 bits.

Abstract: Methods and apparatus relating to a modular exponentiation hardware accelerator with unconstrained operands for public key encryption are described. In an embodiment, a memory stores a base and a modulus. Logic circuitry left shifts the modulus one or more times until a most significant bit of the modulus reaches a threshold value. The base remains unchanged while the logic circuitry left shifts the modulus. Other embodiments are also disclosed and claimed.

Abstract: Technologies for memory and I/O efficient operations on homomorphically encrypted data are disclosed. In the illustrative embodiment, a cloud compute device is to perform operations on homomorphically encrypted data. In order to reduce memory storage space and network and I/O bandwidth, ciphertext blocks can be manipulated as data structures, allowing operands for operations on a compute engine to be created on the fly as the compute engine is performing other operations, using orders of magnitude less storage space and bandwidth.