Patents by Inventor RAGHAVAN KUMAR

RAGHAVAN KUMAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250110735
    Abstract: Techniques for static instruction decoupling for data movement and computer are described. In some examples, hardware support at least includes a plurality of instruction queues to store instructions, wherein each instruction queue of the plurality of instruction queues is dedicated to a separate thread; a local memory to store instructions and/or data for a first thread; a scratchpad memory, coupled to the local memory, to store instructions and/or data for a second thread; and execution resources, coupled to the scratchpad memory, to execute one or more mathematic and/or logical instructions for a third thread.
    Type: Application
    Filed: September 30, 2023
    Publication date: April 3, 2025
    Inventors: AppaRao CHALLAGUNDLA, Adish VARTAK, Christopher WILKERSON, Rosario CAMMAROTA, Raghavan KUMAR, Sanu K. MATHEW, Vasantha SRIRAMBHATLA
  • Publication number: 20250112759
    Abstract: Techniques for side-channel and fault-injection detection in AES are described. In some examples, the detection mechanism includes substitution box (S-box) circuitry, including multiplicative inverse circuitry to receive a masked 8-bit input in Galois field, and to generate a corresponding 8-bit masked output in Galois field, wherein, when there has been no error in the generation of the 8-bit masked output, the 8-bit masked output is to be a multiplicative inverse of the 8-bit masked input; and inverse error detection circuitry to receive the 8-bit masked input and coupled with the S-box circuitry to receive the 8-bit masked output, the inverse error detection circuitry to detect whether an error has occurred in the generation of the 8-bit masked output based at least in part on whether the 8-bit masked output is the multiplicative inverse of the 8-bit masked input.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Raghavan KUMAR, Sanu K. MATHEW, Avinash L Varna
  • Publication number: 20250112757
    Abstract: Examples include techniques for mixed word size multiplication to facilitate operations for relinearization associated with executing a fully homomorphic encryption (FHE) workload. Examples include use of precomputed base conversion factors and decomposing large words or digits to a data size that is equal to or smaller than a machine word size associated with a multiplier datapath to facilitate the operations for relinearization.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Raghavan KUMAR, Sanu K. MATHEW, Adish VARTAK, Christopher B. WILKERSON
  • Publication number: 20250112772
    Abstract: Bandwidth of High Bandwidth Memory (HBM) and scratch pad memory used by an Fully Homomorphic Encryption (FHE) accelerator in a System-on-Chip (SoC) during FHE relinearization is reduced by including a key generator module in the SoC. The key generator module to generate FHE public keys from a seed that is input to the SoC. The seed used by the on-die key generator module to generate FHE relinearization public keys locally within the scratch pad memory units in the SoC.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Sachin TANEJA, Sanu K. MATHEW, Christopher B. WILKERSON, Raghavan KUMAR, Anupam GOLDER
  • Publication number: 20250007687
    Abstract: Techniques for fully homomorphic encryption are described. In some examples, a register file to store polynomials is coupled to a butterfly compute path. The butterfly compute path includes a multiplier coupled to a first input and a second input to multiply the first and second input to, when enabled, generate a multiplication output, a first multiplexer coupled to an output of the multiplier and to the first input to output a selection between the output of the multiplier and the first input, an adder to add, when enabled, a third input to the selected output of the first multiplexer, a subtractor to subtract, when enabled, an output of the multiplier from the third input, and a second multiplexer coupled to an output of the multiplier and to the first input to, when enabled, output a selection between the output of the multiplier and the subtractor.
    Type: Application
    Filed: July 1, 2023
    Publication date: January 2, 2025
    Inventors: Sanu MATHEW, Vikram SURESH, Sachin TANEJA, Raghavan KUMAR, Christopher WILKERSON
  • Publication number: 20250005100
    Abstract: Examples include techniques for contention-free routing for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations routed through a parallel processing device. Examples include a tile array that includes a plurality of tiles arranged in a 2-dimensional mesh interconnect-based architecture. Each tile includes a plurality of compute elements configured to execute NTT or iNTT computations associated with a fully homomorphic encryption workload.
    Type: Application
    Filed: July 1, 2023
    Publication date: January 2, 2025
    Inventors: Raghavan KUMAR, AppaRao CHALLAGUNDLA, Sanu K. MATHEW, Christopher B. WILKERSON, Adish VARTAK, Sachin TANEJA, Minxuan ZHOU, Lalith Dharmesh KETHARESWARAN
  • Publication number: 20250005101
    Abstract: Examples include techniques for twiddle factor generation for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations by a compute element. The compute element can be included in a parallel processing device. Examples include receiving information to generate a twiddle factor for use by the compute element to execute an NTT or an iNTT computation for an N-degree polynomial, obtain data for a power of 2 of a root of unity from a memory resident on a same chip or die as the compute element and generate the twiddle factor using the obtained data based, at least in part, on the received information.
    Type: Application
    Filed: July 1, 2023
    Publication date: January 2, 2025
    Inventors: Sachin TANEJA, Sanu K. MATHEW, Raghavan KUMAR, Nojan SHEYBANI, Vikram B. SURESH
  • Publication number: 20250007688
    Abstract: A reconfigurable compute circuitry to perform Fully Homomorphic Encryption (FHE) enables a full utilization of compute resources and data movement resources by mapping multiple N*1024 polynomials on to a (M*N)*1024 polynomial. To counteract the shuffling of the coefficients during Number-Theoretic-Transforms (NTT) and inverse-NTT operations, compute elements in the compute circuitry operate in a bypass mode that is enabled by a data movement instruction, to convert from the shuffled form to contiguous form without modifying the values of the coefficients.
    Type: Application
    Filed: July 1, 2023
    Publication date: January 2, 2025
    Inventors: Raghavan KUMAR, Sanu K. MATHEW, Sachin TANEJA, Christopher B. WILKERSON, Minxuan ZHOU
  • Publication number: 20250005102
    Abstract: Examples include techniques for twiddle factor generation for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations by a compute element. The compute element can be included in a parallel processing device. Examples include receiving information to generate a twiddle factor for use by the compute element to execute an NTT or an iNTT computation for an N-degree polynomial, obtain data for a power of 2 of a root of unity from a memory resident on a same chip or die as the compute element and generate the twiddle factor using the obtained data based, at least in part, on the received information.
    Type: Application
    Filed: March 8, 2024
    Publication date: January 2, 2025
    Inventors: Sachin TANEJA, Sanu K. MATHEW, Raghavan KUMAR, Nojan SHEYBANI, Vikram B. SURESH
  • Patent number: 12137169
    Abstract: In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: November 5, 2024
    Assignee: Intel Corporation
    Inventors: Santosh Ghosh, Vikram Suresh, Sanu Mathew, Manoj Sastry, Andrew H. Reinders, Raghavan Kumar, Rafael Misoczki
  • Publication number: 20240333471
    Abstract: In one embodiment, a method comprises: combining, in a first adder circuit of a cryptographic engine, a round key with masked plaintext to generate an additively masked input; converting, in a first converter of the cryptographic engine, the additively masked input to a multiplicatively masked input; and performing, in a substitution box circuit of the cryptographic engine, a non-linear inverse operation on the multiplicatively masked input when the multiplicatively masked input is non-zero, and performing the non-linear inverse operation on a random non-zero value when the multiplicatively masked input is zero. Other embodiments are described and claimed.
    Type: Application
    Filed: March 27, 2023
    Publication date: October 3, 2024
    Inventors: Raghavan Kumar, Sanu Mathew, Sachin Taneja
  • Publication number: 20240333472
    Abstract: An apparatus of an aspect includes a substitution box (S-box) circuitry. The S-box circuitry includes multiplicative inverse circuitry. The multiplicative inverse circuitry is to receive an 8-bit input in Galois field and is to generate a corresponding 8-bit output in Galois field. The 8-bit output is to be a multiplicative inverse of the 8-bit input as long as there has been no error in the generation of the 8-bit output. The apparatus also includes error detection circuitry to receive the 8-bit input and that is coupled with the S-box circuitry to receive the 8-bit output. The error detection circuitry to detect whether an error has occurred in the generation of the 8-bit output based at least in part on whether the 8-bit output is the multiplicative inverse of the 8-bit input. Other apparatus, methods, and systems are also disclosed.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Inventors: Raghavan Kumar, Sanu Mathew, Avinash V. Varna, Kirk S. YAP
  • Patent number: 12047485
    Abstract: Apparatus and method for resisting side-channel attacks on cryptographic engines are described herein. An apparatus embodiment includes a cryptographic block coupled to a non-linear low-dropout voltage regulator (NL-LDO). The NL-LDO includes a scalable power train to provide a variable load current to the cryptographic block, randomization circuitry to generate randomized values for setting a plurality of parameters, and a controller to adjust the variable load current provided to the cryptographic block based on the parameters and the current voltage of the cryptographic block. The controller to cause a decrease in the variable load current when the current voltage is above a high voltage threshold, an increase in the variable load current when the current voltage is below a low voltage threshold; and a maximization of the variable load current when the current voltage is below an undervoltage threshold. The cryptographic block may be implemented with arithmetic transformations.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: July 23, 2024
    Assignee: Intel Corporation
    Inventors: Raghavan Kumar, Xiaosen Liu, Harish Krishnamurthy, Sanu Mathew, Vikram Suresh
  • Patent number: 11917053
    Abstract: In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: February 27, 2024
    Assignee: Intel Corporation
    Inventors: Santosh Ghosh, Vikram Suresh, Sanu Mathew, Manoj Sastry, Andrew H. Reinders, Raghavan Kumar, Rafael Misoczki
  • Publication number: 20240007266
    Abstract: In one example an apparatus comprises a first input node to receive a first plaintext input, a second input node to receive a random mask, an advanced encryption standard (AES) engine configurable to operate in one of a first mode in which the random mask is added to the first plaintext input during one or more computations performed by the AES engine, or second mode in which the random mask is not added to the first plaintext input during one or more computations performed by the AES engine. Other examples may be described.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Raghavan Kumar, Vikram B. Suresh, Sanu K. Mathew
  • Publication number: 20240007267
    Abstract: In one example an apparatus comprises a first input node to receive a first plaintext input, a second input node to receive a second plaintext input, a third input node to receive a random mask and an advanced encryption standard (AES) circuitry configurable to operate in one of a first mode in which the random mask is added to the first plaintext input during one or more computations to convert the first plaintext input to a first ciphertext output, or a second mode in which the first plaintext input is converted to a first ciphertext output and the second plaintext input is converted to a second ciphertext output without using the random mask. Other examples may be described.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Raghavan Kumar, Sanu K. Mathew
  • Publication number: 20230401434
    Abstract: An apparatus is described. The apparatus includes a long short term memory (LSTM) circuit having a multiply accumulate circuit (MAC). The MAC circuit has circuitry to rely on a stored product term rather than explicitly perform a multiplication operation to determine the product term if an accumulation of differences between consecutive, preceding input values has not reached a threshold.
    Type: Application
    Filed: August 24, 2023
    Publication date: December 14, 2023
    Applicant: Intel Corporation
    Inventors: Ram KRISHNAMURTHY, Gregory K. CHEN, Raghavan KUMAR, Phil KNAG, Huseyin Ekin SUMBUL
  • Publication number: 20230334006
    Abstract: A compute near memory (CNM) convolution accelerator enables a convolutional neural network (CNN) to use dedicated acceleration to achieve efficient in-place convolution operations with less impact on memory and energy consumption. A 2D convolution operation is reformulated as 1D row-wise convolution. The 1D row-wise convolution enables the CNM convolution accelerator to process input activations row-by-row, while using the weights one-by-one. Lightweight access circuits provide the ability to stream both weights and input rows as vectors to MAC units, which in turn enables modules of the CNM convolution accelerator to implement convolution for both [1×1] and chosen [n×n] sized filters.
    Type: Application
    Filed: June 20, 2023
    Publication date: October 19, 2023
    Inventors: Huseyin Ekin SUMBUL, Gregory K. CHEN, Phil KNAG, Raghavan KUMAR, Ram KRISHNAMURTHY
  • Patent number: 11790217
    Abstract: An apparatus is described. The apparatus includes a long short term memory (LSTM) circuit having a multiply accumulate circuit (MAC). The MAC circuit has circuitry to rely on a stored product term rather than explicitly perform a multiplication operation to determine the product term if an accumulation of differences between consecutive, preceding input values has not reached a threshold.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: October 17, 2023
    Assignee: Intel Corporation
    Inventors: Ram Krishnamurthy, Gregory K. Chen, Raghavan Kumar, Phil Knag, Huseyin Ekin Sumbul
  • Patent number: 11783160
    Abstract: Various systems, devices, and methods for operating on a data sequence. A system includes a set of circuits that form an input layer to receive a data sequence; first hardware computing units to transform the data sequence, the first hardware computing units connected using a set of randomly selected weights, a first hardware computing unit to: receive an input from a second hardware computing unit, determine a weight of a connection between the first and second hardware computing units using an identifier of the second hardware computing unit and a fixed random weight generator, and operate on the input using the weight to determine a state of the first hardware computing unit; and second hardware computing units to operate on states of the first computing units to generate an output based on the data sequence.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: October 10, 2023
    Assignee: Intel Corporation
    Inventors: Phil Knag, Gregory Kengho Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Ram Kumar Krishnamurthy