Abstract: In one embodiment, a method comprises: combining, in a first adder circuit of a cryptographic engine, a round key with masked plaintext to generate an additively masked input; converting, in a first converter of the cryptographic engine, the additively masked input to a multiplicatively masked input; and performing, in a substitution box circuit of the cryptographic engine, a non-linear inverse operation on the multiplicatively masked input when the multiplicatively masked input is non-zero, and performing the non-linear inverse operation on a random non-zero value when the multiplicatively masked input is zero. Other embodiments are described and claimed.

Abstract: An apparatus is described. The apparatus includes a long short term memory (LSTM) circuit having a multiply accumulate circuit (MAC). The MAC circuit has circuitry to rely on a stored product term rather than explicitly perform a multiplication operation to determine the product term if an accumulation of differences between consecutive, preceding input values has not reached a threshold.

Abstract: An on-die key generator includes a pseudo-random number generator (PRNG) and a sampler. The pseudo-random number generator generates integers modulo a power-of-two number, based on an initial seed. The sampler uniformly maps the integers generated by the random number generator (RNG) from the number space of 0?(2n?1) to the ciphertext modulus space of 0?(q?1) by randomly mapping the integers generated by the pseudo-random number generator that are greater than or equal to q to a value inside the range [0, q?1] using additional random bits.

Abstract: Compute circuitry to perform Fully Homomorphic Encryption (FHE) includes a memory system and a compute engine. The compute engine includes tiles organized in an array. The array of tiles in the compute engine provides compute elements to perform polynomial operations for polynomials. Synchronization support is provided by a Compute Engine Control Block (CCB) in the compute circuitry. The Compute Engine Control Block decomposes large data word loads and stores (with data spread across memory channels) into smaller requests for each memory channel. The Compute Engine Control Block uses completion signals received from each memory channel to assess the completion state of the large data word load/store. The Compute Engine Control Block to manage instruction dispatch across all tiles in the array of tiles and to ensure the tiles in the compute engine to operate in lockstep to enable synchronization free communication between the tiles.

Abstract: Examples include techniques for contention-free routing for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations routed through a parallel processing device. Examples include a tile array that includes a plurality of tiles arranged in a 2-dimensional mesh interconnect-based architecture. Each tile includes a plurality of compute elements configured to execute NTT or iNTT computations associated with a fully homomorphic encryption workload. Contention-free routing to include use of grouped or compressed source addresses to be used in routing tables maintained at tiles of the tile array.

Abstract: Examples include techniques for contention-free routing for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations routed through a parallel processing device. Examples include a tile array that includes a plurality of tiles arranged in a 2-dimensional mesh interconnect-based architecture. Each tile includes a plurality of compute elements configured to execute NTT or iNTT computations associated with a fully homomorphic encryption workload. Contention-free routing to include use of selective stalls and destination ports indicated in routing tables maintained at tiles of the tile array can facilitate NTT/iNTT computation throughput through the parallel processing device.

Abstract: An apparatus and method for attack-resistant encryption and decryption. For example, one embodiment of an apparatus comprises: execution circuitry to execute instructions and generate memory access requests including load requests to read data from memory and store requests to store data to memory; and cryptographic circuitry to perform a plurality of rounds of encryption or decryption to encrypt or decrypt the data, respectively, the cryptographic circuitry to perform one or more redundant rounds for a corresponding one or more of the plurality of rounds, the one or more redundant rounds to include spatial or temporal differences relative to the corresponding one or more rounds; the cryptographic circuitry to generate a fault upon detecting a mismatch between an output of a redundant round output and an output of a corresponding round.

Abstract: Efficient generation of uniform random numbers for FHE public key generation across varying prime numbers with different bit width is provided by configuring an xorshift linear feedback shift register (LFSR) based Random Number Generator (RNG) to optimal bit width while maintaining the uniformity properties. The prime value and corresponding xorshift RNG tap locations are used to configure the xorshift LFSR based RNG to generate the random numbers between [0, 2m] where m is configured to generate the next power of 2 corresponding to a selected prime q value. The configuration of the xorshift LFSR based RNG reduces the worst-case rejection rate from 100% to 50% across prime q values from 17 bits to 32 bits.

Abstract: Methods and apparatus relating to a modular exponentiation hardware accelerator with unconstrained operands for public key encryption are described. In an embodiment, a memory stores a base and a modulus. Logic circuitry left shifts the modulus one or more times until a most significant bit of the modulus reaches a threshold value. The base remains unchanged while the logic circuitry left shifts the modulus. Other embodiments are also disclosed and claimed.

Abstract: Technologies for memory and I/O efficient operations on homomorphically encrypted data are disclosed. In the illustrative embodiment, a cloud compute device is to perform operations on homomorphically encrypted data. In order to reduce memory storage space and network and I/O bandwidth, ciphertext blocks can be manipulated as data structures, allowing operands for operations on a compute engine to be created on the fly as the compute engine is performing other operations, using orders of magnitude less storage space and bandwidth.

Abstract: Techniques for side-channel and fault-injection detection in AES are described. In some examples, the detection mechanism includes substitution box (S-box) circuitry, including multiplicative inverse circuitry to receive a masked 8-bit input in Galois field, and to generate a corresponding 8-bit masked output in Galois field, wherein, when there has been no error in the generation of the 8-bit masked output, the 8-bit masked output is to be a multiplicative inverse of the 8-bit masked input; and inverse error detection circuitry to receive the 8-bit masked input and coupled with the S-box circuitry to receive the 8-bit masked output, the inverse error detection circuitry to detect whether an error has occurred in the generation of the 8-bit masked output based at least in part on whether the 8-bit masked output is the multiplicative inverse of the 8-bit masked input.

Abstract: Techniques for static instruction decoupling for data movement and computer are described. In some examples, hardware support at least includes a plurality of instruction queues to store instructions, wherein each instruction queue of the plurality of instruction queues is dedicated to a separate thread; a local memory to store instructions and/or data for a first thread; a scratchpad memory, coupled to the local memory, to store instructions and/or data for a second thread; and execution resources, coupled to the scratchpad memory, to execute one or more mathematic and/or logical instructions for a third thread.

Abstract: Examples include techniques for mixed word size multiplication to facilitate operations for relinearization associated with executing a fully homomorphic encryption (FHE) workload. Examples include use of precomputed base conversion factors and decomposing large words or digits to a data size that is equal to or smaller than a machine word size associated with a multiplier datapath to facilitate the operations for relinearization.

Abstract: Bandwidth of High Bandwidth Memory (HBM) and scratch pad memory used by an Fully Homomorphic Encryption (FHE) accelerator in a System-on-Chip (SoC) during FHE relinearization is reduced by including a key generator module in the SoC. The key generator module to generate FHE public keys from a seed that is input to the SoC. The seed used by the on-die key generator module to generate FHE relinearization public keys locally within the scratch pad memory units in the SoC.

Abstract: Examples include techniques for contention-free routing for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations routed through a parallel processing device. Examples include a tile array that includes a plurality of tiles arranged in a 2-dimensional mesh interconnect-based architecture. Each tile includes a plurality of compute elements configured to execute NTT or iNTT computations associated with a fully homomorphic encryption workload.

Abstract: Examples include techniques for twiddle factor generation for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations by a compute element. The compute element can be included in a parallel processing device. Examples include receiving information to generate a twiddle factor for use by the compute element to execute an NTT or an iNTT computation for an N-degree polynomial, obtain data for a power of 2 of a root of unity from a memory resident on a same chip or die as the compute element and generate the twiddle factor using the obtained data based, at least in part, on the received information.

Abstract: A reconfigurable compute circuitry to perform Fully Homomorphic Encryption (FHE) enables a full utilization of compute resources and data movement resources by mapping multiple N*1024 polynomials on to a (M*N)*1024 polynomial. To counteract the shuffling of the coefficients during Number-Theoretic-Transforms (NTT) and inverse-NTT operations, compute elements in the compute circuitry operate in a bypass mode that is enabled by a data movement instruction, to convert from the shuffled form to contiguous form without modifying the values of the coefficients.

Abstract: Examples include techniques for twiddle factor generation for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations by a compute element. The compute element can be included in a parallel processing device. Examples include receiving information to generate a twiddle factor for use by the compute element to execute an NTT or an iNTT computation for an N-degree polynomial, obtain data for a power of 2 of a root of unity from a memory resident on a same chip or die as the compute element and generate the twiddle factor using the obtained data based, at least in part, on the received information.

Abstract: Techniques for fully homomorphic encryption are described. In some examples, a register file to store polynomials is coupled to a butterfly compute path. The butterfly compute path includes a multiplier coupled to a first input and a second input to multiply the first and second input to, when enabled, generate a multiplication output, a first multiplexer coupled to an output of the multiplier and to the first input to output a selection between the output of the multiplier and the first input, an adder to add, when enabled, a third input to the selected output of the first multiplexer, a subtractor to subtract, when enabled, an output of the multiplier from the third input, and a second multiplexer coupled to an output of the multiplier and to the first input to, when enabled, output a selection between the output of the multiplier and the subtractor.

Abstract: In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.