Abstract: A cloud computing network device is disclosed. The device is configured to receive a request from a joining device for access to the cloud computing network, and in response to the request, authenticate the joining device according to an authentication protocol. The device is also configured to receive from the joining device an indication of one or more items local to the joining device to be made available to other devices on the cloud computing network, and in response to the indication, provide information identifying items to the other devices on the cloud computing network.

Abstract: A cloud computing network device is disclosed. The device is configured to generate output data based on input data, wherein the output data is indicative of the input data, cause data indicative of the input data to be stored in a memory, and respond to instructions to access the input data by accessing the data stored in the memory.

Abstract: A cloud computing network device is disclosed. The device is configured to generate output data based on input data, wherein the output data is indicative of the input data, cause data indicative of the input data to be stored in a memory, and respond to instructions to access the input data by accessing the data stored in the memory.

Abstract: A Dynamic Random Access Memory (DRAM) controller. The DRAM controller includes receiving a plurality of access requests from a plurality of user interfaces to access one or more DRAM devices. Further, the DRAM controller includes storing the plurality of access requests in a Content Addressable Memory (CAM). Furthermore, the DRAM controller includes updating at least one access request of the plurality of access requests to a Next Access Table. In addition, the DRAM controller includes determining at least one paramount access request of the plurality of access requests by a CAM based decision controller for employing a bypass operation in the CAM based decision controller, based on a plurality of pre-defined conditions. Further, the DRAM controller includes issuing the plurality of access requests to the one or more DRAM devices.

Abstract: Method and apparatus to unify all of a persons' data from all his devices and services including without limitation computers, smartphones, online cloud storage services, and offline pluggable hard drives and also including all data that has been shared with said person by others into a virtual cloud for that person which can be accessed, searched, browsed, managed, replicated, backed up from anywhere and any portion of which can be shared with others with fine grain access control lists that control what all the sharee can do. This method and apparatus also including mechanisms to deal with portions of the cloud that may be offline or behind slow links with smart caching and mechanisms to access data on this virtual cloud using the fastest, cheapest, or most reliable means. This virtual cloud also including all services that the person has access to.

Abstract: A method and system for accessing a dynamic random access memory (DRAM) is provided. A memory controller includes a content addressable memory (CAM) based decision control module for determining a next best access request for the DRAM. The CAM based decision control module includes a CAM access storage module for storing access requests, a next access table module for storing the next best access request, and a decision logic module for determining the next best access request based on results from the CAM access storage module and the next access table module. Further, the memory controller includes a DRAM access control interface for implementing signaling required to access the DRAM. The method includes storing access requests in a CAM access storage module. The method includes determining which of the stored access requests is a next best access request. Further, the method includes processing the next best access request.

Abstract: A method of controlling a dynamic random access memory (DRAM) and a DRAM memory controller is provided. An example DRAM memory controller includes a content addressable memory (CAM) based decision control module. The CAM based decision control module includes a CAM access storage module, a next access table module, and a decision logic module. Further, the DRAM memory controller includes a DRAM access control interface. The method includes detecting a request for a read-modify-write operation. The method also includes creating a read access request and a write access request based on the detecting. Further, the method includes prioritizing the read access request and the write access request. Moreover, the method includes executing the read access request and the write access request based on the prioritizing.

Abstract: Embodiments of the present invention relate to portions of a switch fabric having a single logical stage and at least one physical stage. In addition, the data paths and the control paths of the switch fabric can be decoupled thereby allowing additional processing to be performed than would otherwise be the case with control rates that matched the high data rates. In other words, data cells received on high speed links can be spread over many lower speed links; consequently, the data cells can transit the switch fabric at that high speed while the control information associated with the data can be processed at that lower speed. Because the control information can be processed at a lower speed (associated with the control path), the control information can be processed over a greater period of time.

Abstract: An efficient implementation of a digital delay locked loop (DLL) circuit is disclosed. The delay locked loop (DLL) circuit includes a phase detector circuit, a clock divider circuit, a delay, a delay control finite state machine (FSM) and an output low pass filter. The delay includes a coarse delay line and a fine delay line. The coarse delay line delays a signal by a fixed large amount and the fine delay line introduces a smaller precise delay. The delay control FSM adjusts the delay to keep the output signal of the DLL synchronized with the input. The adjustment is averaged over a range of cycle periods in order to avoid adjusting the edges of signal waveform constantly. The low pass filter at the output minimizes the jitter in the output signal.

Abstract: Embodiments of the present invention relate to portions of a switch fabric having a single logical stage and at least one physical stage. In addition, the data paths and the control paths of the switch fabric can be decoupled thereby allowing additional processing to be performed than would otherwise be the case with control rates that matched the high data rates. In other words, data cells received on high speed links can be spread over many lower speed links; consequently, the data cells can transit the switch fabric at that high speed while the control information associated with the data can be processed at that lower speed. Because the control information can be processed at a lower speed (associated with the control path), the control information can be processed over a greater period of time.

Abstract: Embodiments of the present invention relate to portions of a switch fabric having a single logical stage and at least one physical stage. In addition, the data paths and the control paths of the switch fabric can be decoupled thereby allowing additional processing to be performed than would otherwise be the case with control rates that matched the high data rates. In other words, data cells received on high speed links can be spread over many lower speed links; consequently, the data cells can transit the switch fabric at that high speed while the control information associated with the data can be processed at that lower speed. Because the control information can be processed at a lower speed (associated with the control path), the control information can be processed over a greater period of time.

Abstract: Embodiments of the present invention relate to portions of a switch fabric having a single logical stage and at least one physical stage. In addition, the data paths and the control paths of the switch fabric can be decoupled thereby allowing additional processing to be performed than would otherwise be the case with control rates that matched the high data rates. In other words, data cells received on high speed links can be spread over many lower speed links; consequently, the data cells can transit the switch fabric at that high speed while the control information associated with the data can be processed at that lower speed. Because the control information can be processed at a lower speed (associated with the control path), the control information can be processed over a greater period of time.

Abstract: Methods and devices useful in high-speed scalable switching systems include a memoryless switch fabric, per virtual channel queuing, digital phase aligners, randomized and complement connection modes, a mid-point negative acknowledge and output negative acknowledge scheme among other elements. A particular implementation of a routing table and switch element is described in part to illustrate the various techniques and devices of the invention.

Abstract: Methods and devices useful in high-speed scalable switching systems include a memoryless switch fabric, per virtual channel queuing, digital phase aligners, randomized and complement connection modes, a mid-point negative acknowledge and output negative acknowledge scheme among other elements. A particular implementation of a routing table and switch element is described in part to illustrate the various techniques and devices of the invention.