Abstract: A method of forming a gate located above multiple fin regions of a semiconductor device. The method may include removing unwanted fin structures after epitaxially growing junctions.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fin structures on a substrate, the plurality of fin structures including a diffusion region, forming an epitaxial layer on the plurality of fin structures in an area of the diffusion region such that a height of the upper surface of the epitaxial layer over plurality of fin structures is substantially equal to the height of the upper surface of the epitaxial layer between the plurality of fin structures, and planarizing the upper surface of the epitaxial layer by one of etch back and reflow annealing.

Abstract: The present invention relates generally to semiconductor devices, and more particularly, to a structure and method of forming a spacer adjacent to a gate in a fin field effect transistor (FinFET) device without resulting in substrate gouging or a spacer foot. A conformal spacer layer may be formed around a plurality of fins and a gate, wherein the conformal spacer layer may have a thickness above the plurality of fins that is at least one-half the distance between the individual fins. An isotropic etch may be used to remove excess spacer material around the plurality of fins (but not between the fins) and around the gate. An anisotropic etch may be used to remove the remaining spacer material from between the fins and around the gate, leaving a spacer adjacent to the gate without gouging the substrate surface between the fins.

Abstract: A semiconductor device is disclosed. The semiconductor device can include a first dielectric layer disposed on a substrate; a set of bias lines disposed on the first dielectric layer; a second dielectric layer disposed on the first dielectric layer and between the set of bias lines, wherein a thickness of the second dielectric layer is less than a thickness of the first dielectric layer; a patterned semiconductor layer disposed on portions of the second dielectric layer; and a set of devices disposed on the patterned semiconductor layer above the set of bias lines.

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

Abstract: FinFET devices and methods of making the same. A structure includes: a substrate with a buried insulator, a plurality of fins over a recessed buried insulator, and a nitride material filing recessed spaces between the plurality of fins, wherein the plurality of fins remain uncovered by the nitride, and wherein the nitride material does not contact the bottom of the plurality of fins.

Abstract: A FinFET device includes a substrate with a buried insulator, a plurality of fins over the buried insulator, and a nitride material filing spaces between the plurality of fins. At least one sidewall of each of the plurality of fins remain uncovered by the nitride material. The nitride material may also not contact the bottom of the plurality of fins.

Abstract: Embodiments of the present invention provide an electrically controlled optical fuse. The optical fuse is activated electronically instead of by the light source itself. An applied voltage causes the fuse temperature to rise, which induces a transformation of a phase changing material from transparent to opaque. A gettering layer absorbs excess atoms released during the transformation.

Abstract: An on-chip capacitor with enhanced capacitance and a method of forming the same are provided. An epitaxial process is employed to selectively form semiconductor material nodules on portions of a semiconductor material nodule nucleation layer that is present atop a semiconductor substrate. The semiconductor material nodules have an increased surface area for forming a capacitor structure thereon. A metal-insulator-metal capacitor structure is then formed surrounding each semiconductor material nodule. The resultant semiconductor structure (i.e., on-chip capacitor) has enhanced capacitance without increasing the size of the chip or the fabrication cost.

Abstract: The present invention relates generally to semiconductor devices, and more particularly, to a structure and method of reducing external resistance within fin field effect transistor (finFET) devices. A first spacer and a second spacer may be formed adjacent to a gate which may reduce capacitance in a substantial portion of a epitaxial source-drain region while also permitting a portion of the epitaxial source-drain region to be located close to a channel. By reducing capacitance from the gate on the substantial portion of the epitaxial source-drain region, resistance in the epitaxial source-drain region may be reduced which may result in increased device performance.

Abstract: A semiconductor device includes a silicon-on-insulator (SOI) substrate having a buried oxide (BOX) layer, and a plurality of semiconductor fins formed on the BOX layer. The plurality of semiconductor fins include at least one pair of fins defining a BOX region therebetween. Gate lines are formed on the SOI substrate and extend across the plurality of semiconductor fins. Each gate line initially includes a dummy gate and a hardmask. A high dielectric (high-k) layer is formed on the hardmask and the BOX regions. At least one spacer is formed on each gate line such that the high-k layer is disposed between the spacer and the hardmask. A replacement gate process replaces the hardmask and the dummy gate with a metal gate. The high-k layer is ultimately removed from the gate line, while the high-k layer remains on the BOX region.

Abstract: A method of forming a gate located above multiple fin regions of a semiconductor device. The method may include removing unwanted fin structures after epitaxially growing junctions.

Abstract: A method of forming a gate located above multiple fin regions of a semiconductor device. The method may include removing unwanted fin structures after epitaxially growing junctions.

Abstract: The present invention relates generally to semiconductor devices, and more particularly, to a structure and method of forming a spacer adjacent to a gate in a fin field effect transistor (FinFET) device without resulting in substrate gouging or a spacer foot. A conformal spacer layer may be formed around a plurality of fins and a gate, wherein the conformal spacer layer may have a thickness above the plurality of fins that is at least one-half the distance between the individual fins. An isotropic etch may be used to remove excess spacer material around the plurality of fins (but not between the fins) and around the gate. An anisotropic etch may be used to remove the remaining spacer material from between the fins and around the gate, leaving a spacer adjacent to the gate without gouging the substrate surface between the fins.

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

Abstract: The present invention relates generally to semiconductor devices, and more particularly, to a structure and method of reducing external resistance within fin field effect transistor (finFET) devices. A first spacer and a second spacer may be formed adjacent to a gate which may reduce capacitance in a substantial portion of a epitaxial source-drain region while also permitting a portion of the epitaxial source-drain region to be located close to a channel. By reducing capacitance from the gate on the substantial portion of the epitaxial source-drain region, resistance in the epitaxial source-drain region may be reduced which may result in increased device performance.

Abstract: A semiconductor device is disclosed. The semiconductor device can include a first dielectric layer disposed on a substrate; a set of bias lines disposed on the first dielectric layer; a second dielectric layer disposed on the first dielectric layer and between the set of bias lines, wherein a thickness of the second dielectric layer is less than a thickness of the first dielectric layer; a patterned semiconductor layer disposed on portions of the second dielectric layer; and a set of devices disposed on the patterned semiconductor layer above the set of bias lines.

Abstract: A method of forming a quantum well having a conformal epitaxial well on a {100} crystallographic orientated fin. The method may include: forming fins in a {100} crystallographic oriented substrate; forming a conformal well on the fins using epitaxial growth; and forming a conformal barrier on the conformal well using epitaxial growth.

Abstract: Embodiments of present invention provide a method of forming a semiconductor device. The method includes depositing a layer of metal over one or more channel regions of respective one or more transistors in a substrate, the layer of metal having a first region and a second region; lowering height of the first region of the layer of metal; forming an insulating layer over the first region of lowered height, the insulating layer being formed to have a top surface coplanar with the second region of the layer of metal; and forming at least one contact to a source/drain region of the one or more transistors. Structure of the semiconductor device formed thereby is also provided.

Abstract: FinFET devices and methods of making the same. A structure includes: a substrate with a buried insulator, a plurality of fins over the buried insulator, and a nitride material filing spaces between the plurality of fins, wherein the plurality of fins remain uncovered by the nitride.