Patents by Inventor Raghaven MADHAVAN

Raghaven MADHAVAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170046160
    Abstract: Systems and methods of handling a register file include, in a first instruction set architecture (ISA) mode assigning a first subset of tracking resources to logical registers of a first logical register subset for tracking mappings to full granularity and first lower granularity physical registers of a first physical register subset, and assigning a second subset of tracking resources to logical registers of a second logical register subset for tracking mappings to second lower granularity physical registers of the first physical register subset. The second subset of tracking resources are configured for tracking at least the logical registers of the second logical register subset mappings to physical registers of a second physical register subset in a second ISA mode, wherein the second physical register subset is available to the second ISA mode but not the first ISA mode.
    Type: Application
    Filed: March 31, 2016
    Publication date: February 16, 2017
    Inventors: Kiran Ravi SETH, Rodney Wayne SMITH, Yusuf Cagatay TEKMEN, Raghaven MADHAVAN