Patents by Inventor RAGHAVENDRA DEVAPPA SHARMA

RAGHAVENDRA DEVAPPA SHARMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Back power protection circuit
    Patent number: 10938200
    Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Amit Kumar Srivastava, Karthik Ns, Raghavendra Devappa Sharma, Dharmaray Nedalgi, Prasad Bhilawadi
  • BACK POWER PROTECTION CIRCUIT
    Publication number: 20170170646
    Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.
    Type: Application
    Filed: February 27, 2017
    Publication date: June 15, 2017
    Inventors: Amit Kumar SRIVASTAVA, Karthik NS, Raghavendra Devappa SHARMA, Dharmaray NEDALGI, Prasad BHILAWADI
  • Back power protection circuit
    Patent number: 9601916
    Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventors: Amit Kumar Srivastava, Karthik Ns, Raghavendra Devappa Sharma, Dharmaray Nedalgi, Prasad Bhilawadi
  • BACK POWER PROTECTION CIRCUIT
    Publication number: 20160079747
    Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.
    Type: Application
    Filed: September 11, 2014
    Publication date: March 17, 2016
    Inventors: Amit Kumar Srivastava, KARTHIK NS, RAGHAVENDRA DEVAPPA SHARMA, DHARMARAY NEDALGI, PRASAD BHILAWADI