Abstract: A storage device may maintain data reliability between sub-blocks by executing wear leveling operations such that a program-erase count (PEC) difference between sister sub-blocks is reduced. The storage device may include a memory device including blocks, and at least one of the blocks may be divided into sister sub-blocks. The storage device may also include a controller to calculate a sister sub-block threshold and process a wear leveling operation. When executing the wear leveling operation, the controller may select a destination block. The controller may also prioritize a first sister block for a multi-layer cell (MLC) flow when the PEC value of a second sister sub-block is greater than the sister sub-block threshold.

Abstract: A storage device maintains uniform write performance for data written to a memory device including varying block sizes. The storage device includes a balancing module to ensure that free blocks exist in a partition on the memory device and to define a garbage collection threshold based on blocks available in the partition. The storage device also includes a controller to receive host data from a host device, write the host data to the memory device; and relocate the host data in the memory device during a background operation. The controller initiates the background operation on the memory device at the garbage collection threshold and executes the background operation according to a host write-to-relocation write ratio based on a dynamically calculated size of the remaining free blocks in the partition.

Abstract: A storage device may use unused bits in a memory device communicatively coupled to the storage device to reduce resource usage and time on the storage device during background operations. The memory device includes a plane having a redundant column section including unused bits. When the storage device receives instructions from a host device, a controller on the storage device may determine that the instructions are associated with data to be discarded from the memory device and may associate the data to be discarded with fragments in the memory device. The controller may generate relocation information, associate the relocation information with data stored in the memory device, and store the relocation information in the unused bits. During relocation operations, the controller may use the relocation information to determine whether fragments in the memory device include the data to be discarded and/or whether to move data in the memory device.

Abstract: Aspects are provided for optimizing game loading and rendering using an RMB dedicated for predicted host data that is accessible to a host and to a controller of a storage device. The controller obtains a bitmap indicating a status of a buffer in the RMB, receives from the host a read command indicating a logical address, predicts and reads from an NVM host data associated with a predicted logical address that is subsequent to the logical address, and loads the host data in the buffer in the RMB if the buffer is free. Subsequent read commands indicating the predicted logical address may lack PRP addresses in response to the host data being loaded in the RMB, while completion queue elements in response to such commands may include PRP addresses in the RMB where the host data is stored. Thus, command creation and completion overhead may be reduced using the RMB.

Abstract: A storage device performs error handling using asymmetric blocks in a memory device. The memory may be divided into blocks of varying sizes. A controller on the storage device may process instructions by writing data to a first block on the memory device. If the controller determines an error occurred with a write operation to the first block and if the controller is unable to find a second block that is the same size as the first block, the controller may replace the first block with a second block that is larger than the first block. The controller may mark the second block and continue with the write operation.

Abstract: Aspects are provided for optimizing game loading and rendering using an RMB dedicated for predicted host data that is accessible to a host and to a controller of a storage device. The controller obtains a bitmap indicating a status of a buffer in the RMB, receives from the host a read command indicating a logical address, predicts and reads from an NVM host data associated with a predicted logical address that is subsequent to the logical address, and loads the host data in the buffer in the RMB if the buffer is free. Subsequent read commands indicating the predicted logical address may lack PRP addresses in response to the host data being loaded in the RMB, while completion queue elements in response to such commands may include PRP addresses in the RMB where the host data is stored. Thus, command creation and completion overhead may be reduced using the RMB.

Abstract: Aspects of a storage device provide an optimized data relocation scanning process which significantly reduces a number of page reads performed during a block relocation scan by consolidating logical addresses for multiple FMUs in a single FMU. The storage device includes a memory comprising a block including pages and FMUs, and a controller that is configured to store, in one of the FMUs, logical addresses for multiple FMUs. The controller is further configured, in response to a data relocation command, to read the logical addresses from the FMU, to determine at least one of the read logical addresses is mapped to a current FMU in a L2P mapping table, and to relocate data stored at the valid logical addresses in response to the determination. As a result, latency and power consumption associated with data relocation may be significantly reduced and storage device performance may thus be improved.

Abstract: Aspects of the disclosure are directed to a storage device including a memory and a controller. The memory may include a plurality of flash memory blocks such as single level cell (SLC) blocks and multi-level cell (MLC) blocks. The controller may maintain a read count of each of the SLC blocks to determine which of the blocks contains data associated with the highest number of read commands. Based on the read commands, the controller may relocate the associated data into pages of MLC blocks that have a lower number of senses required to read the data stored in those blocks.

Abstract: The present disclosure generally relates to using irregular MetaBlocks (IRMBs) in both host and control pools. The IRMBs are used to ensure efficient wear leveling. Blocks in the control pool are swapped with blocks in the host pool upon exceeding a program-erase count (PEC) threshold. Additionally, the swapping algorithm for IRMBs can be used to ensure an efficient recovery from an ungraceful shutdown (UGSD) event.

Abstract: Aspects of the disclosure are directed to a storage device including a memory and a controller. The memory may include a plurality of flash memory blocks such as single level cell (SLC) blocks and multi-level cell (MLC) blocks. The controller may maintain a read count of each of the SLC blocks to determine which of the blocks contains data associated with the highest number of read commands. Based on the read commands, the controller may relocate the associated data into pages of MLC blocks that have a lower number of senses required to read the data stored in those blocks.

Abstract: The present disclosure generally relates to using irregular MetaBlocks (IRMBs) in both host and control pools. The IRMBs are used to ensure efficient wear leveling. Blocks in the control pool are swapped with blocks in the host pool upon exceeding a program-erase count (PEC) threshold. Additionally, the swapping algorithm for IRMBs can be used to ensure an efficient recovery from an ungraceful shutdown (UGSD) event.

Abstract: Aspects of a storage device provide an optimized data relocation scanning process which significantly reduces a number of page reads performed during a block relocation scan by consolidating logical addresses for multiple FMUs in a single FMU. The storage device includes a memory comprising a block including pages and FMUs, and a controller that is configured to store, in one of the FMUs, logical addresses for multiple FMUs. The controller is further configured, in response to a data relocation command, to read the logical addresses from the FMU, to determine at least one of the read logical addresses is mapped to a current FMU in a L2P mapping table, and to relocate data stored at the valid logical addresses in response to the determination. As a result, latency and power consumption associated with data relocation may be significantly reduced and storage device performance may thus be improved.

Abstract: A storage device having a wide range of operating temperatures is disclosed. Techniques disclosed herein may be used to operate MLC cells at higher temperatures before resorting to thermal throttling. Techniques disclosed herein may be used to operate MLC cells at lower temperatures without needing to pre-heat the storage device. SLC data stored in a first group of memory cells is folded to MLC data stored in a second group of memory cells while an operating temperature is outside a first temperature range. After the operating temperature is within a second temperature range, the data integrity of the MLC data is checked. The SLC data in the first group is folded to MLC data in a third group of memory cells responsive to the MLC data in the second group failing the data integrity check. The foregoing permits the storage device to increase its range in operating temperatures.

Abstract: A storage device having a wide range of operating temperatures is disclosed. Techniques disclosed herein may be used to operate MLC cells at higher temperatures before resorting to thermal throttling. Techniques disclosed herein may be used to operate MLC cells at lower temperatures without needing to pre-heat the storage device. SLC data stored in a first group of memory cells is folded to MLC data stored in a second group of memory cells while an operating temperature is outside a first temperature range. After the operating temperature is within a second temperature range, the data integrity of the MLC data is checked. The SLC data in the first group is folded to MLC data in a third group of memory cells responsive to the MLC data in the second group failing the data integrity check. The foregoing permits the storage device to increase its range in operating temperatures.

Abstract: An apparatus comprising non-volatile memory is configured to access a selected unit of encoded SLC data in the non-volatile memory during a first programming phase of a process of folding data stored at a single bit per memory cell to data stored at multiple bits per memory cell. The apparatus recovers the selected unit of SLC data based on redundancy data formed from units of SLC data that data include the selected unit of SLC data. The apparatus saves the recovered selected unit of SLC data to memory. The apparatus uses the saved recovered unit of SLC data during a second programming phase of folding the data stored at a single bit per memory cell to the data stored at multiple bits per memory cell, thereby saving considerable time in not having to again recover the SLC data using the redundancy data.

Abstract: Aspects of a storage device are provided which allow transfer of data between cells at higher transfer rates based on a temperature of the cells. The storage device includes a memory having a plurality of first and second cells. Each of the second cells are configured to store more bits than each of the first cells. A controller is configured to store data in the first cells in response to a write command from a host device. The controller is further configured to transfer the data from the first cells to the second cells at a higher transfer rate when a temperature of the second cells is above a temperature threshold than when below the temperature threshold.

Abstract: A storage device having a wide range of operating temperatures is disclosed. Techniques disclosed herein may be used to operate MLC cells at higher temperatures before resorting to thermal throttling. Techniques disclosed herein may be used to operate MLC cells at lower temperatures without needing to pre-heat the storage device. SLC data stored in a first group of memory cells is folded to MLC data stored in a second group of memory cells while an operating temperature is outside a first temperature range. After the operating temperature is within a second temperature range, the data integrity of the MLC data is checked. The SLC data in the first group is folded to MLC data in a third group of memory cells responsive to the MLC data in the second group failing the data integrity check. The foregoing permits the storage device to increase its range in operating temperatures.

Abstract: A storage device having a wide range of operating temperatures is disclosed. Techniques disclosed herein may be used to operate MLC cells at higher temperatures before resorting to thermal throttling. Techniques disclosed herein may be used to operate MLC cells at lower temperatures without needing to pre-heat the storage device. SLC data stored in a first group of memory cells is folded to MLC data stored in a second group of memory cells while an operating temperature is outside a first temperature range. After the operating temperature is within a second temperature range, the data integrity of the MLC data is checked. The SLC data in the first group is folded to MLC data in a third group of memory cells responsive to the MLC data in the second group failing the data integrity check. The foregoing permits the storage device to increase its range in operating temperatures.

Abstract: An apparatus comprising non-volatile memory is configured to access a selected unit of encoded SLC data in the non-volatile memory during a first programming phase of a process of folding data stored at a single bit per memory cell to data stored at multiple bits per memory cell. The apparatus recovers the selected unit of SLC data based on redundancy data formed from units of SLC data that data include the selected unit of SLC data. The apparatus saves the recovered selected unit of SLC data to memory. The apparatus uses the saved recovered unit of SLC data during a second programming phase of folding the data stored at a single bit per memory cell to the data stored at multiple bits per memory cell, thereby saving considerable time in not having to again recover the SLC data using the redundancy data.

Abstract: A storage system and method are disclosed for generating a reverse map during a background operation and storing it in a host memory buffer. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to generate a physical-to-logical address map for at least part of the memory as a background operation and send the physical-to-logical address map to a host for storage in volatile memory in the host.