Patents by Inventor Raghavendra Gopalkrishnan

Raghavendra Gopalkrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Block budget enhancement mechanisms for memory
    Patent number: 11714565
    Abstract: A data storage device, in one implementation, includes a memory device having Single Level Cell (SLC) blocks and Multi-Level Cell (MLC) blocks, such as Triple Level Cell (TLC) blocks. If a SLC block is determined to have errors, the SLC block is reallocated as a TLC block. In some implementations, the TLC block is used to store TLC cold data.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: August 1, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Bhanushankar Doni, Raghavendra Gopalkrishnan
  • BLOCK BUDGET ENHANCEMENT MECHANISMS FOR MEMORY
    Publication number: 20230152995
    Abstract: A data storage device, in one implementation, includes a memory device having Single Level Cell (SLC) blocks and Multi-Level Cell (MLC) blocks, such as Triple Level Cell (TLC) blocks. If a SLC block is determined to have errors, the SLC block is reallocated as a TLC block. In some implementations, the TLC block is used to store TLC cold data.
    Type: Application
    Filed: November 18, 2021
    Publication date: May 18, 2023
    Inventors: Bhanushankar Doni, Raghavendra Gopalkrishnan