Patents by Inventor Raghavendra Shirodkar

Raghavendra Shirodkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • STATIC CMOS-BASED COMPACT FULL ADDER CIRCUITS
    Publication number: 20240311082
    Abstract: Provided is an apparatus that includes an integrated circuit including a static complementary metal-oxide-semiconductor based full adder (FA) circuit. The FA circuit comprises a sum generation circuit configured to generate a sum output and a carry output generation circuit configured to generate a carry output. The sum generation circuit comprises a first exclusive-NOR gate and a second exclusive-NOR gate. The carry output generation circuit comprises a first or-and-invert (OAI) gate, a second OAI gate, and a NAND gate. The first OAI gate is configured to receive an output of the NAND gate to generate one of an exclusive-NOR output or a NOR output of a first operand and a second operand. The second OAI gate is configured to receive the output of the NAND gate, an inverse of a carry input, and the generated one of the exclusive-NOR output or the NOR output to produce the carry output.
    Type: Application
    Filed: April 3, 2023
    Publication date: September 19, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Saurabh Shankar ZOND, Debojyoti Banerjee, Abhishek Ghosh, Raghavendra Shirodkar, Rakesh Dimri, Yashaswini H G