Patents by Inventor Raghaw S. Rai

Raghaw S. Rai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method to control uniformity/composition of metal electrodes, silicides on topography and devices using this method
    Patent number: 7611936
    Abstract: A method for depositing metals on surfaces is provided which comprises (a) providing a substrate (103) having a horizontal surface (107) and a vertical surface (105); (b) depositing a first metal layer (109) over the horizontal and vertical surfaces; (c) depositing a layer of polysilicon (111) over the horizontal and vertical surfaces; (d) treating the layer of polysilicon with a plasma such that a residue (113) remaining from the treatment is preferentially formed over the horizontal surfaces rather than the vertical surfaces, and wherein the residue is resistant to a first metal etch; and (e) exposing the substrate to the first metal etch.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: November 3, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, Ross E. Noble, Raghaw S. Rai
  • Method for improving self-aligned silicide extendibility with spacer recess using an aggregated spacer recess etch (ASRE) integration
    Patent number: 7563700
    Abstract: A method is provided for making a silicided gate (209). In accordance with the method, a semiconductor structure (201) is provided which comprises a semiconductor substrate (202), a gate (209) disposed on the semiconductor substrate, and a spacer (219) adjacent to the gate. The structure is subjected to a first etch which exposes a first lateral portion of the gate. An implant (215) is then created in a region adjacent to the spacer. The structure is then subjected to a second etch which exposes a second lateral portion of the gate electrode, and a layer of silicide (225) is formed which extends over the first and second lateral portions of the gate.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: July 21, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Anadi Srivastava, Mark D. Hall, Raghaw S. Rai, Jesse Yanez
  • Method to control uniformity/composition of metal electrodes, silicides on topography and devices using this method
    Publication number: 20080280429
    Abstract: A method for depositing metals on surfaces is provided which comprises (a) providing a substrate (103) having a horizontal surface (107) and a vertical surface (105); (b) depositing a first metal layer (109) over the horizontal and vertical surfaces; (c) depositing a layer of polysilicon (111) over the horizontal and vertical surfaces; (d) treating the layer of polysilicon with a plasma such that a residue (113) remaining from the treatment is preferentially formed over the horizontal surfaces rather than the vertical surfaces, and wherein the residue is resistant to a first metal etch; and (e) exposing the substrate to the first metal etch.
    Type: Application
    Filed: May 11, 2007
    Publication date: November 13, 2008
    Inventors: Leo Mathew, Ross E. Noble, Raghaw S. Rai