Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

Abstract: A receiver suppresses co-channel interference (CCI) from other transmitters and intersymbol interference (ISI) due to channel distortion using “virtual” antennas. The virtual antennas may be formed by (1) oversampling a received signal for each actual antenna at the receiver and/or (1) decomposing a sequence of complex-valued samples into a sequence of inphase samples and a sequence of quadrature samples. In one design, the receiver includes a pre-processor, an interference suppressor, and an equalizer. The pre-processor processes received samples for at least one actual antenna and generates at least two sequences of input samples for each actual antenna. The interference suppressor suppresses co-channel interference in the input sample sequences and provides at least one sequence of CCI-suppressed samples. The equalizer performs detection on the CCI-suppressed sample sequence(s) and provides detected bits. The interference suppressor and equalizer may be operated for one or multiple iterations.

Abstract: A configurable decoder within a receiver (for example, within a wireless communication device) includes numerous decoders. In one mode, the multiple decoders are used to decode different sub-packets of a packet. When one decoder completes decoding the last sub-packet assigned to it of the packet, then that decoder generates a packet done indication. A control circuit receives the packet done indications, and when all the decoders have generated packet done indications then the control circuit initiates an action. In one example, the action is the interrupting of a processor. The processor responds by reading status information from the control circuit, thereby resetting the interrupt. End-of-packet markers are usable to generate packet done indications and to generate EOP interrupts. Similarly, end-of-group markers are usable to generate group done indications and to generate EOG interrupts. The decoder block is configurable to process sub-packets of a packet using either one or multiple decoders.

Abstract: A de-interleaver involves logic that receives a seed and that simultaneously generates from the seed a plurality of reorder indices. The plurality of reorder indices is usable for de-interleaving an incoming stream of interleaved code bits. Each plurality of simultaneously generated reorder indices generated corresponds to a set of simultaneously received code bits in the incoming stream. The reorder indices are converted into physical addresses in parallel and these physical addresses are used to store the set of code bits into a memory. Code bits for multiple sub-packets of different sub-packet sizes are typically present in memory at the same time. The code bits are then read out of memory to form an outgoing stream of de-interleaved code bits. The de-interleaver has a pipelined architecture such that sets of code bits are written into the memory at the same rate that sets of code bits are received onto the de-interleaver.

Abstract: A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.

Abstract: Systems and techniques are disclosed detecting an embedded signal which includes producing a plurality of first correlated values from a portion of the first signal and a second signal, transforming the first correlation values into a plurality of second correlation values related to a frequency content of the first correlation values, and searching for the embedded signal by evaluating the second correlation values. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: Techniques are provided for suppressing interference by taking into account the possible bursty nature of co-channel interference in a communication system. In an aspect, interference levels are separately computed for first and second data portions of a desired signal. The computed interference levels may be used to scale the corresponding data portions for subsequent processing.

Abstract: A graphics engine includes a setup unit and a rendering unit. The setup unit computes coefficients A, B, and C used for interpolating an attribute v of a triangle to be rendered for a graphics image. The setup unit then derives compressed coefficients Ã, {tilde over (B)}, and {tilde over (C)} based on the coefficients A, B, and C. The compressed coefficients have a fixed-point format with R integer bits left of a binary point and T fractional bits right of the binary point, where R>1 and T?0. R is selected based on the number of bits used for attribute v, T is selected based on the screen dimension, and R+T is much less than the number of bits used to represent the coefficients A, B, and C. The rendering unit performs interpolation for the attribute v using the compressed coefficients Ã, {tilde over (B)}, and {tilde over (C)}, and may be implemented with a simple (R+T)-bit non-saturating accumulator.

Abstract: Techniques for detecting adjacent channel interference (ACI) in a wireless communication system are described. Input inphase (I) and quadrature (Q) samples are filtered with a first filter response to obtain filtered I and Q samples. The first filter response is designed to pass signal in an adjacent frequency channel while suppressing signals in a desired frequency channel and non-adjacent frequency channels. Correlations of the filtered I and Q samples are determined. The presence of ACI is detected based on the correlations of the filtered I and Q samples and the power of the input I and Q samples. If ACI is present, then whether the ACI is from a higher frequency channel or a lower frequency channel is determined based on one or more of the correlations. The input I and Q samples are filtered with a second filter response that is adjusted based on the detection of ACI.

Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

Abstract: Systems and techniques are disclosed wherein a gated pilot signal can be acquired by producing a plurality of product values for each of a first and second signal and a generated signal, coherently combining portions of the product values produced from the first signal and noncoherently combining those coherently combined portions to produce a first value, coherently combining portions of the product values produced from the second signal and noncoherently combining those coherently combined portions to produce a second value, and noncoherently combining the first and second values.

Abstract: A system, method and device for frequency acquisition. In particular, the embodiments allow for a mobile telephone to simultaneously receive data and/or voice signals while acquiring a GPS signal for its navigation feature. The system, method and device of the present embodiments employ a digital rotator and a local oscillator in concert to acquire the respective signals, correct any frequency errors associated with those signals, and maintain a local timing reference suitable for receiving and transmitting data through a mobile network while simultaneously providing an accurate location through a GPS system.

Abstract: A receiver according to one embodiment includes a frequency control unit configured to receive a stream of samples including a plurality of received instances of a transmitted signal. The frequency control unit is configured to output a first correction signal (e.g. indicating a rotation) that is based on more than one of the received instances and a second correction signal (e.g. to control an oscillator) that is also based on more than one of the received instances. In some embodiments, a controlled oscillator is used to receive and/or transmit another signal, such as a signal received from a GPS space vehicle. In other embodiments, the received instances are from a GPS signal. In further embodiments, a fixed-frequency oscillator is used, and the second correction signal is used to receive and/or transmit another signal, such as a GPS signal.

Abstract: A graphics engine includes a setup unit and a rendering unit. The setup unit computes coefficients A, B, and C used for interpolating an attribute v of a triangle to be rendered for a graphics image. The setup unit then derives compressed coefficients Ã, {tilde over (B)}, and {tilde over (C)} based on the coefficients A, B, and C. The compressed coefficients have a fixed-point format with R integer bits left of a binary point and T fractional bits right of the binary point, where R>1 and T?0. R is selected based on the number of bits used for attribute v, T is selected based on the screen dimension, and R+T is much less than the number of bits used to represent the coefficients A, B, and C. The rendering unit performs interpolation for the attribute v using the compressed coefficients Ã, {tilde over (B)}, and {tilde over (C)}, and may be implemented with a simple (R+T)-bit non-saturating accumulator.

Abstract: Techniques for deriving interpolated pilot symbols for a gated pilot in a wireless (e.g., IS-856, cdma2000, or W-CDMA) communication system. In one method, first and second recovered pilot symbols for first and second time instances, respectively, are initially obtained (e.g., derived based on pilot bursts for the gated pilot). A phase change induced in the received signal at a third time instance between the first and second time instances is estimated. First and second phase-rotated symbols are next derived based on the first and second recovered pilot symbols and the estimated induced phase change. Interpolated pilot symbols between the first and third time instances are then derived (e.g., using linear interpolation) based on the first recovered pilot symbol and the first phase-rotated symbol. Similarly, interpolated pilot symbols between the third and second time instances are derived based on the second phase-rotated symbol and the second recovered pilot symbol.

Abstract: Techniques to acquire and track pilots in a CDMA system. In an aspect, frequency acquisition of a number of signal instances (i.e., multipaths) in a received signal may be achieved concurrently based on a frequency control loop (RAFC) maintained for each finger processor of a rake receiver. Upon successful acquisition, frequency tracking of acquired multipaths may be achieved based on a combination of a frequency control loop (VAFC) maintained for an oscillator used for downconverting the received signal and the RAFCs for the finger processors. In a tracking mode, the VAFC tracks the average frequency of the acquired multipaths by adjusting the frequency of the oscillator. The RAFC of each finger processor tracks the residual frequency error (e.g., due to Doppler frequency shift) of the individual acquired multipath by adjusting the frequency of a complex sinusoidal signal used in a rotator within the finger processor.

Abstract: Techniques to search for pilots over code space in a CDMA system. In one aspect, the pilot search is performed using a number of substages, and the search windows for each substage are selected such that the relevant code space is searched while reducing search time. In one specific implementation, two substages are used to search for pilots. The detect substage searches through (e.g., fixed-size) search windows to detect for peaks in the received signal. The dwell substage then searches through (e.g., variable-size) search windows to re-evaluate the detected peaks and remove noise peaks. The dwell windows may be formed such that a code space as small as possible is searched (to reduce search time) but large enough to account for possible drift in the detected peaks. Variable number of peaks may be provided by the dwell substage for the variable-size dwell windows.

Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

Abstract: A receiver suppresses co-channel interference (CCI) from other transmitters and intersymbol interference (ISI) due to channel distortion using “virtual” antennas. The virtual antennas may be formed by (1) oversampling a received signal for each actual antenna at the receiver and/or (1) decomposing a sequence of complex-valued samples into a sequence of inphase samples and a sequence of quadrature samples. In one design, the receiver includes a pre-processor, an interference suppressor, and an equalizer. The pre-processor processes received samples for at least one actual antenna and generates at least two sequences of input samples for each actual antenna. The interference suppressor suppresses co-channel interference in the input sample sequences and provides at least one sequence of CCI-suppressed samples. The equalizer performs detection on the CCI-suppressed sample sequence(s) and provides detected bits. The interference suppressor and equalizer may be operated for one or multiple iterations.

Abstract: Techniques to acquire pilots over code space and/or frequency errors. In one aspect, pilot acquisition is performed using a number of substages, and some of the substages are pipelined and performed in parallel using different processing elements. A searcher initially searches over a designated code space to find peaks, and these peaks may be re-evaluated. Finger processors then attempt to acquire the candidate peaks. The searcher may be operated to search for the next set of peaks while the finger processors process the current set of peaks. In another aspect, the full range of frequency errors for the pilots is divided into a number of frequency bins. A multi-stage scheme is used to evaluate the bins, and may employ pipelining and parallel processing such that a search for peaks in the next bin is performed while acquisition of peaks found for the current bin is attempted.