Patents by Inventor Raghu G
Raghu G has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220365206Abstract: Systems and methods are provided for interrogating a moving acoustic source using radar and processing data using a selection of motion compensation techniques adapted from synthetic aperture radar (SAR) to remove the effects of linear and nonlinear target motion so that the range-Doppler map retains only vibration information in the Doppler dimension. Vibration and sound waveforms can thus be selectively reproduced at specific ranges directly from the radar baseband waveform, without the need for additional complex analysis or audio processing.Type: ApplicationFiled: August 18, 2021Publication date: November 17, 2022Inventors: Christopher T. Rodenbeck, Joshua B. Beun, Ronald D. Lipps, Raghu G. Raj
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Patent number: 11189027Abstract: Disclosed subject matter relates to Peripheral Blood Smear (PBS) that determines an area to be scanned in PBS for analysis. A PBS analysing system captures a focused image at each of plurality of positions in the PBS and determines Quality Indicators (QIs) in focused image. Further, a region is identified in PBS where QIs of focused image satisfy predefined QI threshold limits, as a monolayer region of PBS and determines an initiation point in monolayer region based on cell count value and co-ordinates of each of the plurality of positions located in the monolayer region. Finally, the area to be scanned in monolayer region is determined based on the initiation point and a predefined scan pattern. Determining the area to be scanned yields accurate and faster results.Type: GrantFiled: May 15, 2018Date of Patent: November 30, 2021Assignee: Sigtuple Technologies Private LimitedInventors: Shreepad Potadar, Dheeraj Mundhra, Abhishek Shukla, Raghu G, Amrutha Muralidharan, Deepak Kapoor, Vijay Muralidharan, Nivedita Muthusubramanian, Bharath Cheluvaraju, Apurv Anand, Tathagato Rai Dastidar, Rohit Kumar Pandey
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Patent number: 11120583Abstract: Systems and methods are provided for imaging that demonstrably outperform previous approaches (especially compressive sensing based approaches). Embodiments of the present disclosure provide and solve an imaging cost function via a stochastic approximation approach. By doing so, embodiments of the preset disclosure provide a significant means of generalization and flexibility to adapt to different application domains while being competitive in terms of computational complexity.Type: GrantFiled: October 29, 2019Date of Patent: September 14, 2021Assignee: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Raghu G. Raj, John Mckay, Vishal Monga
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Patent number: 11112854Abstract: Operating pulsed latches on a variable power supply including turning on a first power rail powering a first latch of an integrated circuit, wherein the first latch is a pulsed latch; turning on a second power rail powering a second latch of the integrated circuit, wherein the second latch is operatively coupled to the first latch; performing a scan operation using the first latch and the second latch; turning off the first power rail powering the first latch; and performing a functional operation using the second latch, wherein the first power rail powering the first latch is off during the functional operation.Type: GrantFiled: June 5, 2019Date of Patent: September 7, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven M. Douskey, Raghu G. Gopalakrishnasetty, Mary P. Kusko, Hari Krishnan Rajeev, James D. Warnock
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Patent number: 11029403Abstract: Systems and method are provided for three-dimensional (3D) imaging by using Doppler and interferometric processing techniques for general planar phased arrays. Systems and methods according to embodiments of the present disclosure incorporate motion compensation techniques in a way that utilizes the full aperture of a phase array. Embodiments of the present disclosure can be applied to a variety of different radar imaging modalities, including X-band and millimeter wave (MMW) regimes.Type: GrantFiled: December 18, 2018Date of Patent: June 8, 2021Assignee: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Raghu G. Raj, Christopher T. Rodenbeck
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Patent number: 10816599Abstract: Method and apparatus to test an integrated circuit includes retrieving power distribution data relating to an integrated circuit and designating a segment that includes at least one component of the integrated circuit. A switching limit associated with the segment may be set based on the power distribution data. Processes further generate a testing pattern that includes the determined switching limit associated with the segment.Type: GrantFiled: January 16, 2019Date of Patent: October 27, 2020Assignee: International Business Machines CorporationInventors: Steven M. Douskey, Raghu G. Gopalakrishnasetty, Sumit Panigrahi, Mary P. Kusko
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Patent number: 10746794Abstract: Aspects include a method for logic built-in self-testing (LBIST) for use in an integrated circuit with scan chains. The method includes programming a product control generator and a pattern generator with an LBIST pattern comprising at least a number of loops. The LBIST pattern is executed by generating scan-in test values for scan chains with the pattern generator and controlling at least one test parameter with the product control generator. Scan-out responses are collected from the scan chains in a signature register, and a start request is received from a chip tester. The LBIST is started in response to the start request. Test summary data is reported to the chip tester before the whole number of loops has been executed.Type: GrantFiled: June 13, 2016Date of Patent: August 18, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Satya R. S. Bhamidipati, Raghu G. Gopalakrishnasetty, Mary P. Kusko, Cedric Lichtenau
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Patent number: 10739401Abstract: Aspects include a system having logic built-in self-test (LBIST) circuitry for use in an integrated circuit with scan chains. The system includes a pattern generator configured for generating scan-in test values for said scan chains; a signature register configured for collecting scan-out responses from said scan chains after a clock sequence; an on-product control generator configured for controlling at least one test parameter; one or more microcode array or memory elements configured to receive inputs to initialize fields in the microcode array or memory elements; and a test controller. The test controller includes a reader component configured for reading test parameters from a field of the microcode array or the memory elements; and a programming component configured for configuring the on-product control generator and the pattern generator with a LBIST pattern according to the read test parameters.Type: GrantFiled: June 25, 2018Date of Patent: August 11, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Satya R. S. Bhamidipati, Raghu G. Gopalakrishnasetty, Mary P. Kusko, Cedric Lichtenau
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Publication number: 20200225283Abstract: Method and apparatus to test an integrated circuit includes retrieving power distribution data relating to an integrated circuit and designating a segment that includes at least one component of the integrated circuit. A switching limit associated with the segment may be set based on the power distribution data. Processes further generate a testing pattern that includes the determined switching limit associated with the segment.Type: ApplicationFiled: January 16, 2019Publication date: July 16, 2020Inventors: Steven M. DOUSKEY, Raghu G. GOPALAKRISHNASETTY, Sumit PANIGRAHI, Mary P. KUSKO
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Patent number: 10649028Abstract: Aspects include a method for logic built-in self-testing (LBIST) for use in an integrated circuit with scan chains. The method includes programming a product control generator and a pattern generator with an LBIST pattern comprising at least a number of loops. The LBIST pattern is executed by generating scan-in test values for scan chains with the pattern generator and controlling at least one test parameter with the product control generator. Scan-out responses are collected from the scan chains in a signature register, and a start request is received from a chip tester. The LBIST is started in response to the start request. Test summary data is reported to the chip tester before the whole number of loops has been executed.Type: GrantFiled: January 5, 2016Date of Patent: May 12, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Satya R. S. Bhamidipati, Raghu G. Gopalakrishnasetty, Mary P. Kusko, Cedric Lichtenau
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Publication number: 20200134888Abstract: Systems and methods are provided for imaging that demonstrably outperform previous approaches (especially compressive sensing based approaches). Embodiments of the present disclosure provide and solve an imaging cost function via a stochastic approximation approach. By doing so, embodiments of the preset disclosure provide a significant means of generalization and flexibility to adapt to different application domains while being competitive in terms of computational complexity.Type: ApplicationFiled: October 29, 2019Publication date: April 30, 2020Inventors: Raghu G. Raj, John Mckay, Vishal Monga
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Patent number: 10545190Abstract: Embodiments include techniques for using circuit structures for resolving random testability, the techniques includes analyzing a logic structures of a circuit design, and identifying the logic structures of the circuit that are random resistant structures. The techniques also include replacing the logic structures with random testable structures, and performing a test of the circuit design.Type: GrantFiled: November 8, 2017Date of Patent: January 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Raghu G. GopalaKrishnaSetty, Mary P. Kusko, Spencer K. Millican
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Patent number: 10527674Abstract: Embodiments include techniques for using circuit structures for resolving random testability, the techniques includes analyzing a logic structures of a circuit design, and identifying the logic structures of the circuit that are random resistant structures. The techniques also include replacing the logic structures with random testable structures, and performing a test of the circuit design.Type: GrantFiled: August 21, 2017Date of Patent: January 7, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Raghu G. GopalaKrishnaSetty, Mary P. Kusko, Spencer K. Millican
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Patent number: 10521381Abstract: A method for self-moderating bus arbitration for access to a common bus is provided. The method may include receiving, by a bus arbiter, a request from a master device, wherein the received request includes a priority value set by the master device. The method may also include identifying the priority value from the received transaction request. The method may then include determining an insertion point within a priority table based on comparing the identified priority value to a table entry priority value associated with each table entry within the priority table. The method may further include inserting a new entry into the priority table based on the determined insertion point. The method may also include identifying a highest priority entry within the priority table. The method may then include serving the identified highest priority entry.Type: GrantFiled: May 28, 2019Date of Patent: December 31, 2019Assignee: International Business Machines CorporationInventors: Raghu G. GopalaKrishnaSetty, Venkatasreekanth Prudvi
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Publication number: 20190286221Abstract: Operating pulsed latches on a variable power supply including turning on a first power rail powering a first latch of an integrated circuit, wherein the first latch is a pulsed latch; turning on a second power rail powering a second latch of the integrated circuit, wherein the second latch is operatively coupled to the first latch; performing a scan operation using the first latch and the second latch; turning off the first power rail powering the first latch; and performing a functional operation using the second latch, wherein the first power rail powering the first latch is off during the functional operation.Type: ApplicationFiled: June 5, 2019Publication date: September 19, 2019Inventors: STEVEN M. DOUSKEY, Raghu G. Gopalakrishnasetty, MARY P. KUSKO, Hari Krishnan Rajeev, JAMES D. WARNOCK
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Publication number: 20190278728Abstract: A method for self-moderating bus arbitration for access to a common bus is provided. The method may include receiving, by a bus arbiter, a request from a master device, wherein the received request includes a priority value set by the master device. The method may also include identifying the priority value from the received transaction request. The method may then include determining an insertion point within a priority table based on comparing the identified priority value to a table entry priority value associated with each table entry within the priority table. The method may further include inserting a new entry into the priority table based on the determined insertion point. The method may also include identifying a highest priority entry within the priority table. The method may then include serving the identified highest priority entry.Type: ApplicationFiled: May 28, 2019Publication date: September 12, 2019Inventors: Raghu G. GopalaKrishnaSetty, Venkatasreekanth Prudvi
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Patent number: 10386912Abstract: Operating pulsed latches on a variable power supply including turning on a first power rail powering a first latch of an integrated circuit, wherein the first latch is a pulsed latch; turning on a second power rail powering a second latch of the integrated circuit, wherein the second latch is operatively coupled to the first latch; performing a scan operation using the first latch and the second latch; turning off the first power rail powering the first latch; and performing a functional operation using the second latch, wherein the first power rail powering the first latch is off during the functional operation.Type: GrantFiled: January 12, 2017Date of Patent: August 20, 2019Assignee: International Business Machines CorporationInventors: Steven M. Douskey, Raghu G. Gopalakrishnasetty, Mary P. Kusko, Hari Krishnan Rajeev, James D. Warnock
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Publication number: 20190187275Abstract: Systems and method are provided for three-dimensional (3D) imaging by using Doppler and interferometric processing techniques for general planar phased arrays. Systems and methods according to embodiments of the present disclosure incorporate motion compensation techniques in a way that utilizes the full aperture of a phase array. Embodiments of the present disclosure can be applied to a variety of different radar imaging modalities, including X-band and millimeter wave (MMW) regimes.Type: ApplicationFiled: December 18, 2018Publication date: June 20, 2019Inventors: Raghu G. Raj, Christopher T. Rodenbeck
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Patent number: 10303631Abstract: A method for self-moderating bus arbitration for access to a common bus is provided. The method may include receiving, by a bus arbiter, a request from a master device, wherein the received request includes a priority value set by the master device. The method may also include identifying the priority value from the received transaction request. The method may then include determining an insertion point within a priority table based on comparing the identified priority value to a table entry priority value associated with each table entry within the priority table. The method may further include inserting a new entry into the priority table based on the determined insertion point. The method may also include identifying a highest priority entry within the priority table. The method may then include serving the identified highest priority entry.Type: GrantFiled: March 17, 2016Date of Patent: May 28, 2019Assignee: International Business Machines CorporationInventors: Raghu G. GopalaKrishnaSetty, Venkatasreekanth Prudvi
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Patent number: 10216885Abstract: A method includes receiving a circuit design comprising an input scan chain comprising a plurality of latches connected by one or more scan connections, dividing the plurality of latches into one or more clusters, determining a number of scan controls for each cluster, placing the determined scan controls in selected locations; and adjusting the scan connections based on the scan control location. A corresponding computer system and computer program product are also disclosed.Type: GrantFiled: December 5, 2017Date of Patent: February 26, 2019Assignee: International Business Machines CorporationInventors: Raghu G. GopalaKrishnaSetty, Ankit N. Kagliwal, Sridhar H. Rangarajan, James D. Warnock