Abstract: Embodiments herein describe the design of a scan cell within an integrated circuit. The scan cell operates in either a test mode or a normal functional mode according to a scan enable signal. The scan cell comprises delay logic including a plurality of delay elements, e.g., a plurality of transistors. The delay logic activates the delay elements only when the scan cell operates in the test mode. The delay elements are activated to change a scan latency of the scan cell. The scan latency of the scan cell is increased to mitigate or prevent hold violations.

Abstract: A method includes receiving a circuit design comprising an input scan chain comprising a plurality of latches connected by one or more scan connections, dividing the plurality of latches into one or more clusters, determining a number of scan controls for each cluster, placing the determined scan controls in selected locations; and adjusting the scan connections based on the scan control location. A corresponding computer system and computer program product are also disclosed.

Abstract: A method includes receiving a circuit design comprising an input scan chain comprising a plurality of latches connected by one or more scan connections, dividing the plurality of latches into one or more clusters, determining a number of scan controls for each cluster, placing the determined scan controls in selected locations; and adjusting the scan connections based on the scan control location. A corresponding computer system and computer program product are also disclosed.

Abstract: Embodiments herein describe the design of a scan cell within an integrated circuit. The scan cell comprises a memory element, e.g., a flip-flop, and a plurality of output buffer stages. The scan cell also comprises selection logic, e.g., a plurality of transistors. The selection logic selectively activates and deactivates one or more of the plurality of output buffer stages in response to a scan enable signal to change an output latency of the scan cell. The scan cell operates in either a test mode or a normal functional mode according to the scan enable signal. The output latency of the scan cell is changed to mitigate or prevent hold violations.

Abstract: Embodiments herein describe the design of a scan cell within an integrated circuit. The scan cell operates in either a test mode or a normal functional mode according to a scan enable signal. The scan cell comprises delay logic including a plurality of delay elements, e.g., a plurality of transistors. The delay logic activates the delay elements only when the scan cell operates in the test mode. The delay elements are activated to change a scan latency of the scan cell. The scan latency of the scan cell is increased to mitigate or prevent hold violations.

Abstract: A method for self-moderating bus arbitration for access to a common bus is provided. The method may include receiving, by a bus arbiter, a request from a master device, wherein the received request includes a priority value set by the master device. The method may also include identifying the priority value from the received transaction request. The method may then include determining an insertion point within a priority table based on comparing the identified priority value to a table entry priority value associated with each table entry within the priority table. The method may further include inserting a new entry into the priority table based on the determined insertion point. The method may also include identifying a highest priority entry within the priority table. The method may then include serving the identified highest priority entry.

Abstract: Aspects include a method for logic built-in self-testing (LBIST) for use in an integrated circuit with scan chains. The method includes programming a product control generator and a pattern generator with an LBIST pattern comprising at least a number of loops. The LBIST pattern is executed by generating scan-in test values for scan chains with the pattern generator and controlling at least one test parameter with the product control generator. Scan-out responses are collected from the scan chains in a signature register, and a start request is received from a chip tester. The LBIST is started in response to the start request. Test summary data is reported to the chip tester before the whole number of loops has been executed.

Abstract: Aspects include a method for logic built-in self-testing (LBIST) for use in an integrated circuit with scan chains. The method includes programming a product control generator and a pattern generator with an LBIST pattern comprising at least a number of loops. The LBIST pattern is executed by generating scan-in test values for scan chains with the pattern generator and controlling at least one test parameter with the product control generator. Scan-out responses are collected from the scan chains in a signature register, and a start request is received from a chip tester. The LBIST is started in response to the start request. Test summary data is reported to the chip tester before the whole number of loops has been executed.

Abstract: Aspects include a system having logic built-in self-test (LBIST) circuitry for use in an integrated circuit with scan chains. The system includes a pattern generator configured for generating scan-in test values for said scan chains; a signature register configured for collecting scan-out responses from said scan chains after a clock sequence; an on-product control generator configured for controlling at least one test parameter; one or more microcode array or memory elements configured to receive inputs to initialize fields in the microcode array or memory elements; and a test controller. The test controller includes a reader component configured for reading test parameters from a field of the microcode array or the memory elements; and a programming component configured for configuring the on-product control generator and the pattern generator with a LBIST pattern according to the read test parameters.

Abstract: A method includes receiving a circuit design comprising an input scan chain comprising a plurality of latches connected by one or more scan connections, dividing the plurality of latches into one or more clusters, determining a number of scan controls for each cluster, placing the determined scan controls in selected locations; and adjusting the scan connections based on the scan control location. A corresponding computer system and computer program product are also disclosed.

Abstract: A scan chain of an integrated circuit is disclosed, including a plurality of scannable storage elements and a control test point having a scan latch and an integrated clock gate (ICG) with clock, functional enable (FE) and scan enable (SE) inputs, and a gated clock output. The ICG may respond to an SE input active state, in a serial scan mode allowing the gated clock output to change. The ICG may also be operated in a scan capture mode, responding to an SE input inactive state, in which the gated clock output is inhibited from changing in response to a low FE input level. The ICG's gated clock output may be coupled to the scan latch clock input, which may hold its data output at a fixed level in response to ICG's gated clock output being inhibited from changing during the scan capture operation.

Abstract: A scan chain of an integrated circuit is disclosed, including a plurality of scannable storage elements and a control test point having a scan latch and an integrated clock gate (ICG) with clock, functional enable (FE) and scan enable (SE) inputs, and a gated clock output. The ICG may respond to an SE input active state, in a serial scan mode allowing the gated clock output to change. The ICG may also be operated in a scan capture mode, responding to an SE input inactive state, in which the gated clock output is inhibited from changing in response to a low FE input level. The ICG's gated clock output may be coupled to the scan latch clock input, which may hold its data output at a fixed level in response to ICG's gated clock output being inhibited from changing during the scan capture operation.

Abstract: A control test point (CTP) of an integrated circuit scan chain includes a scan latch and an integrated clock gate (ICG). The ICG includes clock, functional enable (FE) and scan enable (SE) inputs, and a gated clock output. The ICG can respond to an SE input active state, in a serial scan mode allowing the gated clock output to change. The ICG can also be operated in a scan capture mode, responding to an SE input inactive state, in which the gated clock output is inhibited from changing in response to a low FE input level. The ICG's gated clock output is coupled to the scan latch clock input, which holds its data output at a fixed level in response to ICG's gated clock output being inhibited from changing during the scan capture operation.

Abstract: A method for creating an architecture to support Q-gating for launch-off-shift (LOS) scan testing using a plurality of flip-flops is provided. The method may include applying a common clock signal to each clock input of the plurality of flip-flops and applying a gated scan enable signal to each scan enable input of the plurality of flip-flops. The method may further include applying a global scan enable signal directly to each of a plurality of Q-gates corresponding to each of the plurality of flip-flops, wherein the global scan enable signal traverses a signal path that bypasses combinational logic located between any two flip-flops of the plurality of flip-flops.

Abstract: A scan chain of an integrated circuit is disclosed, including a plurality of scannable storage elements and a control test point having a scan latch and an integrated clock gate (ICG) with clock, functional enable (FE) and scan enable (SE) inputs, and a gated clock output. The ICG may respond to an SE input active state, in a serial scan mode allowing the gated clock output to change. The ICG may also be operated in a scan capture mode, responding to an SE input inactive state, in which the gated clock output is inhibited from changing in response to a low FE input level. The ICG's gated clock output may be coupled to the scan latch clock input, which may hold its data output at a fixed level in response to ICG's gated clock output being inhibited from changing during the scan capture operation.

Abstract: A method for creating an architecture to support Q-gating for launch-off-shift (LOS) scan testing using a plurality of flip-flops is provided. The method may include applying a common clock signal to each clock input of the plurality of flip-flops and applying a gated scan enable signal to each scan enable input of the plurality of flip-flops. The method may further include applying a global scan enable signal directly to each of a plurality of Q-gates corresponding to each of the plurality of flip-flops, wherein the global scan enable signal traverses a signal path that bypasses combinational logic located between any two flip-flops of the plurality of flip-flops.

Abstract: A processor-implemented method for selective Q-gating flip-flops in a plurality of flip-flops contained in a design is provided. The method may include determining a maximum width, a maximum depth, and a maximum congestion value in the design and determining a relative width, a relative depth, and a relative congestion value for each of the plurality of flip-flops in the design. The method may further include determining grade values for each of the plurality of flip-flops in the design based on a ratio between the relative width, the relative depth and the relative congestion value, and the maximum width, the maximum depth, and the maximum congestion value, respectively and determining an overall summed value for each of the plurality of flip-flops. Then the method may sort the plurality of flip-flops based on the overall summed value for the plurality of flip-flops according to magnitude.

Abstract: Aspects of the invention provide for a method of delay defect testing in integrated circuits. In one embodiment, the method includes: generating at least one test pattern based on a transition fault model type; evaluating a dynamic voltage drop for the at least one pattern during a capture cycle and generating a voltage drop value for the at least one test pattern; performing a static timing analysis, using the voltage drop value for the at least one test pattern; evaluating a plurality of paths in the at least one pattern; and masking each path that fails to meet a timing requirement.