Abstract: Aspects of the present disclosure generally relate to wireless communications and, more particularly, to performing channel estimation with modifications for improved system performance. Aspects generally include receiving, at a user equipment (UE), reference signals from a base station in a current subframe, and performing channel estimation, wherein the channel estimation is based at least in part on the reference signals received in the current subframe, a mobility characteristic of the UE, and a configuration of subframes prior to the current subframe.

Abstract: A method for sending an acknowledgment message in a wireless communication system is disclosed. A first signal is received before receiving a second signal from a transmitter. Decoded first data is extracted from the first signal. A third signal is produced by encoding and modulating the decoded first data. The second signal is demodulated to produce second symbols. The third signal and the second symbols are correlated.

Abstract: Methods and apparatus for correcting frequency errors between a carrier frequency of a signal received by a wireless device and a reference frequency local to the device. For certain aspects, such a method generally includes receiving a signal in a receiver having an LO producing a reference frequency, a radio frequency (RF) phase-locked loop (PLL), and a digital rotator, estimating a frequency difference between a carrier frequency of the received signal and the LO reference frequency, and applying the estimated frequency difference to the RF PLL and the digital rotator.

Abstract: An apparatus including a configurable demodulation architecture which includes a control module and a demodulation engine. The control module includes a set of one or more control fields. The demodulation engine includes a spatial whitening module, a Minimum Mean Square Estimation (MMSE) module, at least a first Maximal Ratio Combining (MRC) module, and at least one multiplexer. Further, the multiplexer is coupled to the instruction module and controlled based on the control fields to select at least one of the MMSE module or MRC module.

Abstract: A plurality of predetermined amplifier gain states for a low noise amplifier (LNA) are run during initial acquisition in a time division duplex (TDD) system. Acquisition of a received signal is determined based on searching across the plurality of predetermined amplifier gain states. Forcing the amplifier gain into a set of predetermined gain states affords quicker resolution of initial acquisition for setting the gain of the LNA, which in TDD systems is complicated due to an uncertain uplink/downlink timeline that precludes continuous operation of a gain setting algorithm run in the LNA.

Abstract: In embodiments, user equipment (UE) is configured to acquire automatic gain control (AGC) of an analog RF front end by maintaining a plurality of M×N AGC loops in which the output of the power detector drives input of a gain state machine after a predetermined delay. Each of the loops corresponds to a different periodic set of tasks of (1/M) subframe in length. In each of the loops, the gain is determined by a power measurement taken ((M×N)+1) tasks ago. A synchronization signal, such as a Primary Synchronization Signal, occurs early in Time Division Duplex (TDD) subframes that follow selected downlink subframes. The periodicity of the selected subframes is N. This allows the UE to converge on proper AGC gain for downlink subframes through a relatively short search, such as a binary search. The UE can then decode the synchronization signal and acquire network timing.

Abstract: Systems and methods for computing log likelihood ratios in a communication system are described. A demodulated symbol may be received. A set of scalars may be determined based on a modulation order, a signal-to-noise ratio for the symbol, and a bit of the symbol. At least one log likelihood ratio for the bit may be approximated using a piecewise linear process based on the scalars and the symbol.

Abstract: Methods, apparatus and articles of manufacture are disclosed that provide for early termination based on transport block fail for acknowledgement bundling in time division duplex. In one embodiment, a method for operating a communication device is provided. In this embodiment, the communication device decodes a downlink subframe that is part of a bundle of subframes. If it detects a CRC failure in the subframe, it inhibits decoding of at least one other subframe in the bundle if present and reports the failure to the sending node. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the disclosed subject matter. Therefore, it is to be understood that it should not be used to interpret or limit the scope or the meaning of the claims.

Abstract: An improved processing engine for performing Fourier transforms includes an instruction processor configured to process sequential instruction software commands and a Fourier transform engine coupled to the instruction processor. The Fourier transform engine is configured to perform Fourier transforms on a serial stream of data. The Fourier transform engine is configured to receive configuration information and operational data from the instruction processor via a set of software tasks.

Abstract: Within a receiver, a channel estimation mechanism involves a hardware interpolator. In a first mode, narrowband pilot values are analyzed to generate channel parameters that are supplied to the interpolator such that the interpolator generates channel estimate values. The channel estimate values are used to demodulate a tile of a frame. In a second mode, broadband pilot values are supplied to an IFFT, thereby generating time domain values. After time domain processing, an FFT is employed to generate intermediate channel estimate values. These intermediate values are analyzed to determine channel parameters, which in turn are supplied to the hardware interpolator so that the interpolator generates a larger number of channel estimate values. After phase adjustment, the channel estimate values are used in demodulation. Use of the interpolator in the broadband mode allows the FFT employed to be of a smaller order, and to consume less power and/or processing resources.

Abstract: A multi-stage interference suppression receiver includes a short equalizer section configured to operate on a first portion of a received signal received over a channel to produce a first equalized signal and a first estimate of the channel, a channel estimator section configured to operate on the first equalized signal to produce a second equalized signal, the channel estimator section comprising a linear estimator and a non-linear estimator, a long equalizer section configured to operate on a second portion of the received signal to produce a first estimate of symbols in the received signal and a second estimate of the channel and an interference canceller section configured to operate on the first estimate of symbols in the received signal to generate a second estimate of symbols in the received signal based on, at least in part, the second estimate of the channel.

Abstract: An apparatus and method for enhanced downlink processing of received channels in a mobile communications system is described, containing a buffer for control data and traffic data, a demapper engine with at least two independently operating demappers for demapping the control and traffic data, a log-likelihood-ratio (LLR) buffer for supporting memory segments accessible by the demapper engine, a decoder engine containing decoders, each of the decoders operating on data from selected memory segment(s) of the LLR buffer, and an arbitrator providing control of at least one of the demapper engine, LLR buffer, and decoder engine. At least one of the decoders is suited for decoding control data and another one of the decoders is suited for decoding traffic data. By partitioning the decoding as such, an increase in downlink throughput can be obtained.

Abstract: A de-interleaver generates a plurality of De-interleaved Reorder Physical (DRP) addresses to simultaneously write a corresponding plurality of LLR values into a multi-banked memory such that not more than one LLR value is written into each bank of the multi-banked memory at a time. A sequence of such parallel writes results in the LLR values of a transmission of a sub-packet being stored in the memory. Address translation performed during generation of the DRP addresses causes the LLR values to be stored within the banks such that a decoder can read LLR values out of the memory in a de-interleaved sequence. Each memory location of a bank is a word-location for storing multiple related LLR values, where one LLR value is stored along with its parity values. The ability to simultaneously write to multiple LLR values is used to clear locations in a fast and efficient manner.

Abstract: Pipeline automatic gain control (AGC) processing is conducted by a mobile device when preparing for reception of one or more synchronization signals in a cell, when the mobile device has no knowledge of a timing and/or configuration of the synchronization signals in the cell. The mobile device triggers selection of a particular set of pipeline AGC processing operations and sets an amplifier with an amplifier gain setting determined by the selected set of pipeline AGC processing operations.

Abstract: Aspects of the present disclosure generally relate to wireless communications and, more particularly, to performing channel estimation with modifications for improved system performance. Aspects generally include receiving, at a user equipment (UE), reference signals from a base station in a current subframe, and performing channel estimation, wherein the channel estimation is based at least in part on the reference signals received in the current subframe, a mobility characteristic of the UE, and a configuration of subframes prior to the current subframe.

Abstract: An apparatus operable in a wireless communication system, the apparatus may include an FFT symbol buffer and a demapping device. The FFT symbol buffer can feed FFT symbol data derived from received communication signals to a channel estimation device and a shared buffer. The channel estimation device can also provide intermediate data to the shared buffer. The intermediate data may be in tile form and can be derived from the FFT symbol data. Further, the intermediate data can be stored in the shared buffer. The demapping device can extract the intermediate data from the shared buffer in various forms including sub-packet form.

Abstract: A demodulation mask bitmap includes binary mask values. Each mask value corresponds to an input resource element to a demodulator. For each mask value of a first state, a demodulation engine of the demodulator is not clocked and the demodulator outputs a zero-valued resource element. For each mask value of a second state, the demodulation engine is clocked, the input resource element is demodulated, and the demodulator outputs a demodulated resource element. A demodulation mask bitmap is designed to mask pilot resource elements and corrupted resource elements. Power is conserved by not clocking the demodulation engine for corrupted and pilot resource elements. Subsequent LLR generation and decode operations are simplified. Decoder performance is improved because the decoder does not decode LLR values derived from corrupted resource elements and/or resource elements not relevant to the reconstruction of a communicated message.

Abstract: In embodiments, a fast Fourier transform (FFT) engine includes a series of stages, each stage containing a butterfly and a data normalization device configured to scale output of the stage's butterfly. The scaling factors are adjusted, for example, periodically or on as-needed basis, so that the dynamic range of the butterflies and the buffers is increased for a given bit-width, or the bit-width of these devices is decreased for the same dynamic range. Additionally, bit-width of other buffer(s) is decreased because of the scaling of the data.

Abstract: In embodiments, user equipment (UE) is configured to acquire automatic gain control (AGC) of an analog RF front end by maintaining a plurality of M×N AGC loops in which the output of the power detector drives input of a gain state machine after a predetermined delay. Each of the loops corresponds to a different periodic set of tasks of (1/M) subframe in length. In each of the loops, the gain is determined by a power measurement taken ((M×N)+1) tasks ago. A synchronization signal, such as a Primary Synchronization Signal, occurs early in Time Division Duplex (TDD) subframes that follow selected downlink subframes. The periodicity of the selected subframes is N. This allows the UE to converge on proper AGC gain for downlink subframes through a relatively short search, such as a binary search. The UE can then decode the synchronization signal and acquire network timing.

Abstract: Methods and apparatus for correcting frequency errors between a carrier frequency of a signal received by a wireless device and a reference frequency local to the device. For certain aspects, such a method generally includes receiving a signal in a receiver having an LO producing a reference frequency, a radio frequency (RF) phase-locked loop (PLL), and a digital rotator, estimating a frequency difference between a carrier frequency of the received signal and the LO reference frequency, and applying the estimated frequency difference to the RF PLL and the digital rotator.