Abstract: A method for removing offset in a receiver of an integrated circuit (IC) includes: determining digital codes of differential input voltages of an amplifier in a first receiving lane of the receiver; comparing the digital codes to a digital code corresponding to an optimum common mode voltage (VCM) of the receiver; according to the comparison, determining a bias code for adjusting both the differential input voltages to match the optimum VCM; and inputting the bias code to a bias circuit of the receiver. The first receiving lane of the receiver includes a plurality of amplifiers. The method steps are repeated for each amplifier of the plurality of amplifiers, and then repeated for all receiving lanes of the IC.

Abstract: The controller includes a first equalizer, a first detector, a second detector, a multiplexer, a data clock generator, and a second equalizer. The first equalizer is configured to receive and equalize the input data. The first detector is configured to detect optimum phase of the input data. The optimum phase of the input data represents the input data peak. The second detector is configured to generate an envelope data according to the input data and detect peak of envelop with respect to sampling phase. The data clock generator is configured to generate the recovered data clock. The second equalizer is configured to generate the recovered data. The multiplexer is configured to generate an offset value according to the input data peak and the envelope data peak. The offset value represents the recovered data clock having an optimum sampling frequency and an optimum sampling phase.

Abstract: An apparatus comprises a programmable delay line (PDL) to receive a pulse-width modulation (PWM) signal as input and to generate a first output; a selection unit to provide PWM signal or its inverted version as a second output; and a sequential unit coupled to the PDL to sample the second output with the first output and to generate a pulse-frequency modulation (PFM) output. A voltage regulator comprises mutually coupled on-die inductors for coupling to a load; a bridge coupled to the mutually coupled on-die inductors, including a low-side switch and a high-side switch; a PWM controller for controlling the low-side and high-side switches during a first load current; and a PFM controller for controlling the low-side and high-side switches during a second load current, the second load current being smaller than the first load current, the PFM controller comprising a comparator and a first PDL coupled to the comparator.

Abstract: Described is a soft-start scheme for a voltage regulator. The apparatus comprises: a first voltage regulator to provide regulated voltage to an output node coupled to a load, the first voltage regulator operable to be in open loop via a bypass unit, the first voltage regulator including a comparator; and a second voltage regulator, coupled to the first voltage regulator, operable to be in closed loop, via the bypass unit, to provide a reference voltage for the comparator of the first voltage regulator.

Abstract: Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.

Abstract: Described is an apparatus that comprises: a programmable delay line (PDL) to receive a pulse-width modulation (PWM) signal as input and to generate a first output; a selection unit operable to provide PWM signal or its inverted version as a second output; and a sequential unit coupled to the PDL, the sequential unit to sample the second output with the first output, the sequential unit to generate a pulse-frequency modulation (PFM) output.

Abstract: Described is an apparatus that comprises: a programmable delay line (PDL) to receive a pulse-width modulation (PWM) signal as input and to generate a first output; a selection unit operable to provide PWM signal or its inverted version as a second output; and a sequential unit coupled to the PDL, the sequential unit to sample the second output with the first output, the sequential unit to generate a pulse-frequency modulation (PFM) output.

Abstract: Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.

Abstract: Described is a soft-start scheme for a voltage regulator. The apparatus comprises: a first voltage regulator to provide regulated voltage to an output node coupled to a load, the first voltage regulator operable to be in open loop via a bypass unit, the first voltage regulator including a comparator; and a second voltage regulator, coupled to the first voltage regulator, operable to be in closed loop, via the bypass unit, to provide a reference voltage for the comparator of the first voltage regulator.

Abstract: Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.

Abstract: Described is a soft-start scheme for a voltage regulator. The apparatus comprises: a first voltage regulator to provide regulated voltage to an output node coupled to a load, the first voltage regulator operable to be in open loop via a bypass unit, the first voltage regulator including a comparator; and a second voltage regulator, coupled to the first voltage regulator, operable to be in closed loop, via the bypass unit, to provide a reference voltage for the comparator of the first voltage regulator.

Abstract: Described is an apparatus that comprises: a programmable delay line (PDL) to receive a pulse-width modulation (PWM) signal as input and to generate a first output; a selection unit operable to provide PWM signal or its inverted version as a second output; and a sequential unit coupled to the PDL, the sequential unit to sample the second output with the first output, the sequential unit to generate a pulse-frequency modulation (PFM) output.

Abstract: Described is a soft-start scheme for a voltage regulator. The apparatus comprises: a first voltage regulator to provide regulated voltage to an output node coupled to a load, the first voltage regulator operable to be in open loop via a bypass unit, the first voltage regulator including a comparator; and a second voltage regulator, coupled to the first voltage regulator, operable to be in closed loop, via the bypass unit, to provide a reference voltage for the comparator of the first voltage regulator.