Abstract: A voltage controlled current source provides controlled current to a current controlled oscillator in a high frequency phase-locked loop clock generator. The voltage controlled current source receives a first control signal and a set of second control signals indicative of a phase difference between the output signal of the clock signal generator and a reference frequency. It uses those control signals to adjust the current-controlled oscillator. A level shifter coupled to the current-controlled oscillator amplifies the oscillator signals to full rail and adjusts the duty cycle at its output to 50% to produce the clock signal generator output signal.

Abstract: A phased lock loop (PLL) clock circuit generates a clock signal at 1x the desired clock frequency while maintaining substantially a 50% duty cycle. A first loop provides a feedback signal to maintain clock frequency, while a second loop provides a feedback signal and controls duty cycle. Two clock signals from a ring oscillator are fed to a level shifter, where each clock signal triggers a respective rising or trailing edge of the output clock signal. The level shifter is provided with a delay for controlling timing of the trailing edge of the output clock signal. The output clock signal is fed to a equi-current buffer where a charge pump, driven by the output clock signal, charges and discharges a capacitor in proportion to the duty cycle of the output clock signal, producing a feedback control voltage. The feedback control voltage is applied to the delay of the level shifter to maintain a substantially 50% duty cycle.

Abstract: An oscillator runaway detection circuit is provided with a synchronous delay line such that energy saving or sleep modes of operation are not mischaracterized as oscillator runaway. A Schmitt trigger monitors oscillator control voltage at a filter capacitor. If the control voltage is below a predetermined limit, indicating a possible runaway condition, a signal is output to a synchronous delay line. The output of the Schmitt trigger is propagated through the synchronous delay line comprising a plurality of flip-flops clocked by the system reference clock. The output of the synchronous delay line drives a transistor which in turn may charge the filter capacitor to reduce the control voltage and thus lower the frequency of the oscillator. A one-shot coupled to the clock tree monitors for clock activity in the clock tree.

Abstract: An apparatus and method for instantaneously stretching multi-phase clock signals includes a delay line to generate a plurality of multi-phase clock signals. An instantaneous signal stretch logic circuit is connected to the delay line. The instantaneous signal stretch logic circuit transforms the plurality of multi-phase clock signals into stretched multi-phase clock signals in response to a filter capacitor analog signal and a digital stretch signal. Multiple embodiments of the instantaneous signal stretch logic circuit are disclosed. However, each embodiment includes dual current control paths with a single current control path responsive to the digital stretch signal, which is preferably a single bit value.

Abstract: A low-loss, low-inductance metal interconnect for an electrical signal in a microcircuit comprises a plurality of spaced-apart generally parallel metal interconnect lines disposed in a plane over an insulating layer. The metal interconnect lines are interleaved with and electrically insulated from a plurality of spaced-apart generally parallel metal lines disposed in the plane. The metal interconnect lines together comprise a signal interconnect path, and the metal lines are coupled to a fixed voltage potential, such as ground.

Abstract: A sequential phase-frequency detector circuit using precharged logic and a minimum number of transistors is suitable for use in a delay locked loop because of insensitivity to a stuck delay line output signal. The detector receives standard REFERENCE and LOCAL input signals and provides UP and DOWN output signals for control of a charge pump. In one embodiment, the detector includes a pulse generator for isolating the reset of the UP output signal from a stuck delay line output. This feature permits the UP output to be turned ON while the LOCAL input is stuck at a high level. The circuit exhibits improved gain at phase differences of less than 20 pico-seconds, resulting in reduced phase jitter. The isolating feature minimizes frequency acquisition time in applications in which the frequency of the REFERENCE signal is sometimes substantially reduced, such as during an Energy-Star.TM. power-conserving or Slow modes, which typically causes the delay line output to become stuck.