Patents by Inventor Raghunath PUTIKAM

Raghunath PUTIKAM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240097011
    Abstract: A method includes forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked over a substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure uncovered by the dummy gate structure; performing a selective etching process to laterally recess the first semiconductor layers, including injecting a hydrogen-containing gas from a first gas source of a processing tool to the first semiconductor layers and the second semiconductor layers; and injecting an F2 gas from a second gas source of the processing tool to the first semiconductor layers and the second semiconductor layers; forming inner spacers on opposite end surfaces of the laterally recessed first semiconductor layers of the fin structure; and replacing the dummy gate structure and the first semiconductor layers with a metal gate structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED
    Inventors: Han-Yu LIN, Fang-Wei LEE, Kai-Tak LAM, Raghunath PUTIKAM, Tzer-Min SHEN, Li-Te LIN, Pinyen LIN, Cheng-Tzu YANG, Tzu-Li LEE, Tze-Chung LIN
  • Patent number: 11855192
    Abstract: A method includes forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over a substrate. A dummy gate structure is formed across the fin structure. The exposed second portions of the fin structure are removed. A selective etching process is performed, using a gas mixture including a hydrogen-containing gas and a fluorine-containing gas, to laterally recess the first semiconductor layers. Inner spacers are formed on opposite end surfaces of the laterally recessed first semiconductor layers. Source/drain epitaxial structures are formed on opposite end surfaces of the second semiconductor layers. The dummy gate structure is removed to expose the first portion of the fin structure. The laterally recessed first semiconductor layers are removed. A gate structure is formed to surround each of the second semiconductor layers.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: December 26, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED
    Inventors: Han-Yu Lin, Fang-Wei Lee, Kai-Tak Lam, Raghunath Putikam, Tzer-Min Shen, Li-Te Lin, Pinyen Lin, Cheng-Tzu Yang, Tzu-Li Lee, Tze-Chung Lin
  • Publication number: 20230260847
    Abstract: Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 17, 2023
    Inventors: Wei-Yip LOH, Yan-Ming TSAI, Yi-Ning TAI, Raghunath PUTIKAM, Hung-Yi HUANG, Hung-Hsu CHEN, Chih-Wei CHANG
  • Patent number: 11676868
    Abstract: Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: June 13, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yip Loh, Yan-Ming Tsai, Yi-Ning Tai, Raghunath Putikam, Hung-Yi Huang, Hung-Hsu Chen, Chih-Wei Chang
  • Publication number: 20230054633
    Abstract: Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.
    Type: Application
    Filed: August 19, 2021
    Publication date: February 23, 2023
    Inventors: Wei-Yip LOH, Yan-Ming TSAI, Yi-Ning TAI, Raghunath PUTIKAM, Hung-Yi HUANG, Hung-Hsu CHEN, Chih-Wei CHANG
  • Publication number: 20220173224
    Abstract: A method includes forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over a substrate. A dummy gate structure is formed across the fin structure. The exposed second portions of the fin structure are removed. A selective etching process is performed, using a gas mixture including a hydrogen-containing gas and a fluorine-containing gas, to laterally recess the first semiconductor layers. Inner spacers are formed on opposite end surfaces of the laterally recessed first semiconductor layers. Source/drain epitaxial structures are formed on opposite end surfaces of the second semiconductor layers. The dummy gate structure is removed to expose the first portion of the fin structure. The laterally recessed first semiconductor layers are removed. A gate structure is formed to surround each of the second semiconductor layers.
    Type: Application
    Filed: January 19, 2021
    Publication date: June 2, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC Nanjing Company Limited
    Inventors: Han-Yu LIN, Fang-Wei LEE, Kai-Tak LAM, Raghunath PUTIKAM, Tzer-Min SHEN, Li-Te LIN, Pinyen LIN, Cheng-Tzu YANG, Tzu-Li LEE, Tze-Chung LIN