Patents by Inventor Raghunath Singanamalla
Raghunath Singanamalla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240074159Abstract: A variety of applications can include apparatus having a memory device with metal digit lines for various digit line contacts for a memory array in an integrated process flow of the metal lines with metal contacts of transistors in a periphery to the memory array region. In the integrated process flow, material of the metal digit lines can be used as the metal contacts to the transistors in the periphery to the memory array region. In various embodiments, a metal contact can contact a metal gate of a transistor in the periphery or contact a metal barrier region, where the metal barrier region is above and contacting the metal gate and is structured without including polysilicon. Sacrificial polysilicon can be used to protect the gate of the transistor during processing in the memory array region.Type: ApplicationFiled: August 22, 2023Publication date: February 29, 2024Inventors: Shivani Srivastava, Russell Allen Benson, Raghunath Singanamalla
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Publication number: 20240074160Abstract: A variety of applications can include apparatus having a memory device structured from integrated processing of a memory array of the memory device with a periphery to the memory array. The memory device can be implemented with transistors formed in the periphery, where metal gates of the transistors are structured without polysilicon regions between the metal gates and metal contacts for the metal gates. The integrated processing can provide step height reduction between the memory array and the periphery to the memory array of a memory device, with the elimination of polysilicon on the gate stack of transistors in the periphery. The step height reduction in the memory device can lower overlap capacitance.Type: ApplicationFiled: August 22, 2023Publication date: February 29, 2024Inventors: Shivani Srivastava, Russell Allen Benson, Raghunath Singanamalla, Jaydeb Goswami
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Publication number: 20240074166Abstract: A variety of applications can include apparatus having a memory device with metal digit lines coupled to various digit line contacts for a memory array in an integrated process flow of the metal lines with metal contacts of transistors in a periphery to the memory array region, with a metal silicide formed on the gates of the transistors. The metal silicide for each transistor can be coupled to the metal contact for the transistor. In the integrated process flow, material of the metal digit lines can be used as the metal contact to the transistors in the periphery to the memory array region. The metal silicide can be formed by conversion of polysilicon formed on the memory array region and the periphery to the memory array region in the integrated process flow.Type: ApplicationFiled: August 22, 2023Publication date: February 29, 2024Inventors: Shivani Srivastava, Raghunath Singanamalla, Russell Allen Benson
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Publication number: 20240074161Abstract: A variety of applications can include apparatus having a memory device with digit line contacts disposed in a dielectric and metal digit lines coupled to various of the digit line contacts by at most one metal barrier above the dielectric. Material of the metal digit lines is used as a contact metal to a transistor in a periphery to the memory array region, where the transistor is coupled to the metal contact by multiple barrier metals on polysilicon on the transistor. An integration flow of metallization for periphery devices to a memory array and digit lines can be implemented to allow separate barrier metal formation between the memory array and the periphery, while still using the same material as the main conductor. Barrier metals can be formed for the periphery and the memory array region and then cleared from the memory array region before forming the main conductor.Type: ApplicationFiled: August 22, 2023Publication date: February 29, 2024Inventors: Russell Allen Benson, Shivani Srivastava, Jaydip Guha, Raghunath Singanamalla
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Patent number: 11094697Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.Type: GrantFiled: November 7, 2018Date of Patent: August 17, 2021Assignee: Micron Technology, Inc.Inventors: Gloria Yang, Suraj J. Mathew, Raghunath Singanamalla, Vinay Nair, Scott J. Derner, Michael Amiel Shore, Brent Keeth, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Patent number: 10854611Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.Type: GrantFiled: May 15, 2019Date of Patent: December 1, 2020Assignee: Micron Technology, Inc.Inventors: Suraj J. Mathew, Kris K. Brown, Raghunath Singanamalla, Vinay Nair, Fawad Ahmed, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Patent number: 10847516Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.Type: GrantFiled: July 2, 2019Date of Patent: November 24, 2020Assignee: Micron Technology, Inc.Inventors: Suraj J. Mathew, Raghunath Singanamalla, Fawad Ahmed, Kris K. Brown, Vinay Nair, Gloria Yang, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Publication number: 20190326292Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.Type: ApplicationFiled: July 2, 2019Publication date: October 24, 2019Applicant: Micron Technology, Inc.Inventors: Suraj J. Mathew, Raghunath Singanamalla, Fawad Ahmed, Kris K. Brown, Vinay Nair, Gloria Yang, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Publication number: 20190267379Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.Type: ApplicationFiled: May 15, 2019Publication date: August 29, 2019Applicant: Micron Technology, Inc.Inventors: Suraj J. Mathew, Kris K. Brown, Raghunath Singanamalla, Vinay Nair, Fawad Ahmed, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Patent number: 10361204Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.Type: GrantFiled: June 12, 2018Date of Patent: July 23, 2019Assignee: Micron Technology, Inc.Inventors: Suraj J. Mathew, Raghunath Singanamalla, Fawad Ahmed, Kris K. Brown, Vinay Nair, Gloria Yang, Fatma Arzum Slmsek-Ege, Diem Thy N. Tran
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Patent number: 10319724Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.Type: GrantFiled: July 12, 2018Date of Patent: June 11, 2019Assignee: Micron Technology, Inc.Inventors: Suraj J. Mathew, Kris K. Brown, Raghunath Singanamalla, Vinay Nair, Fawad Ahmed, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Publication number: 20190088652Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.Type: ApplicationFiled: November 7, 2018Publication date: March 21, 2019Applicant: Micron Technology, Inc.Inventors: Gloria Yang, Suraj J. Mathew, Raghunath Singanamalla, Vinay Nair, Scott J. Derner, Michael Amiel Shore, Brent Keeth, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Patent number: 10157926Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.Type: GrantFiled: July 31, 2017Date of Patent: December 18, 2018Assignee: Micron Technology, Inc.Inventors: Gloria Yang, Suraj J. Mathew, Raghunath Singanamalla, Vinay Nair, Scott J. Derner, Michael Amiel Shore, Brent Keeth, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Publication number: 20180331107Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.Type: ApplicationFiled: July 12, 2018Publication date: November 15, 2018Applicant: Micron Technology, Inc.Inventors: Suraj J. Mathew, Kris K. Brown, Raghunath Singanamalla, Vinay Nair, Fawad Ahmed, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Publication number: 20180301454Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.Type: ApplicationFiled: June 12, 2018Publication date: October 18, 2018Applicant: Micron Technology, Inc.Inventors: Suraj J. Mathew, Raghunath Singanamalla, Fawad Ahmed, Kris K. Brown, Vinay Nair, Gloria Yang, Fatma Arzum SImsek-Ege, Diem Thy N. Tran
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Patent number: 10079235Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.Type: GrantFiled: July 31, 2017Date of Patent: September 18, 2018Assignee: Micron Technology, Inc.Inventors: Suraj J. Mathew, Raghunath Singanamalla, Fawad Ahmed, Kris K. Brown, Vinay Nair, Gloria Yang, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Patent number: 10056386Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.Type: GrantFiled: July 31, 2017Date of Patent: August 21, 2018Assignee: Micron Technology, Inc.Inventors: Suraj J. Mathew, Kris K. Brown, Raghunath Singanamalla, Vinay Nair, Fawad Ahmed, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Publication number: 20180061837Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.Type: ApplicationFiled: July 31, 2017Publication date: March 1, 2018Inventors: Suraj J. Mathew, Kris K. Brown, Raghunath Singanamalla, Vinay Nair, Fawad Ahmed, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Publication number: 20180061836Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.Type: ApplicationFiled: July 31, 2017Publication date: March 1, 2018Inventors: Suraj J. Mathew, Raghunath Singanamalla, Fawad Ahmed, Kris K. Brown, Vinay Nair, Gloria Yang, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
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Publication number: 20180061835Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.Type: ApplicationFiled: July 31, 2017Publication date: March 1, 2018Inventors: Gloria Yang, Suraj J. Mathew, Raghunath Singanamalla, Vinay Nair, Scott J. Derner, Michael Amiel Shore, Brent Keeth, Fatma Arzum Simsek-Ege, Diem Thy N. Tran