Abstract: Integrated circuit structures having gate volume reduction, and methods of fabricating integrated circuit structures having gate volume reduction, are described. For example, an integrated circuit structure includes a sub-fin structure beneath a stack of nanowires, the stack of nanowires having a first side and a second side. A dielectric backbone structure is along the first side of the stack of nanowires. The dielectric backbone structure has a bottom above a bottom of the sub-fin. A gate electrode is over the stack of nanowires and is along the second side of the stack of nanowires. A gate dielectric structure is between the gate electrode and the stack of nanowires.

Abstract: Integrated circuit structures having backside self-aligned conductive source or drain contacts, and methods of fabricating integrated circuit structures having backside self-aligned conductive source or drain contacts, are described. For example, an integrated circuit structure includes a sub-fin structure over a vertical stack of horizontal nanowires. An epitaxial source or drain structure is laterally adjacent and coupled to the vertical stack of horizontal nanowires. A conductive source or drain contact is laterally adjacent to the sub-fin structure and is on and in contact with the epitaxial source or drain structure. The conductive source or drain contact does not extend around the epitaxial source or drain structure.