Abstract: Switching cells and decoupling capacitors in an integrated circuit design may be assessed to ensure voltage stability during high-speed switching events. Assessment of the switching cells and decoupling capacitors may include identifying the locations of the switching cells and the decoupling capacitors and dividing the integrated circuit design into a number of equally sized bins. Selected bins for each switching cell may be identified. The selected bin for each switching cell may be assessed, along with one or more bins neighboring the selected bin, to determine if a sufficient number of decoupling capacitors are available in these bins to provide voltage stability for each switching cell in the integrated circuit design.

Abstract: Switching cells and decoupling capacitors in an integrated circuit design may be assessed to ensure voltage stability during high-speed switching events. Assessment of the switching cells and decoupling capacitors may include identifying the locations of the switching cells and the decoupling capacitors and dividing the integrated circuit design into a number of equally sized bins. Selected bins for each switching cell may be identified. The selected bin for each switching cell may be assessed, along with one or more bins neighboring the selected bin, to determine if a sufficient number of decoupling capacitors are available in these bins to provide voltage stability for each switching cell in the integrated circuit design.

Abstract: In an embodiment, the design flow is modified to avoid the flattening process but still accurately annotate the transistors with stress parameters. The location-based stress parameters may be generated, but may not be provided to the LVS tool. Instead, a hierarchical LVS process may be performed, black-boxing lower level blocks that already have stress parameter assignments, preserving hierarchy, etc. The output database from LVS thus includes a cross reference between layout devices and schematic devices, as well as locations of the schematic devices. The database may then be queried for the transistors in the non-flattened design, and the stress parameters may be assigned to the transistors based on the location-based stress parameters. In this fashion the stress parameters may be assigned to the desired transistors, permitting annotation of these parameters into the schematics, without flattening the design and doing unnecessary work on blocks to be skipped.

Abstract: A system and method for analyzing the timing requirements of a memory array are disclosed. The memory cell circuitry used in the original memory array may utilize two bi-directional passgate transistors which are both used during read and write operations on the memory cell, e.g., where signals can flow across the passgate transistors in two directions. A model of the memory array may be created according to a memory cell model that uses uni-directional passgate transistors. Modeling the memory array with uni-directional circuitry may enable a static timing analysis tool to determine the critical path through the memory array. Once the critical path has been determined from the model of the memory array, a dynamic simulation of the critical path in the original memory array may be performed to accurately determine the timing requirements of the original memory array.

Abstract: A system and method for analyzing the timing requirements of a memory array are disclosed. The memory cell circuitry used in the original memory array may utilize two bi-directional passgate transistors which are both used during read and write operations on the memory cell, e.g., where signals can flow across the passgate transistors in two directions. A model of the memory array may be created according to a memory cell model that uses uni-directional passgate transistors. Modeling the memory array with uni-directional circuitry may enable a static timing analysis tool to determine the critical path through the memory array. Once the critical path has been determined from the model of the memory array, a dynamic simulation of the critical path in the original memory array may be performed to accurately determine the timing requirements of the original memory array.