Patents by Inventor Raghuveer Makala
Raghuveer Makala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210397170Abstract: Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).Type: ApplicationFiled: September 2, 2021Publication date: December 23, 2021Applicant: SanDisk Technologies LLCInventors: Fei Zhou, Cheng-Chung Chu, Raghuveer Makala
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Patent number: 10741572Abstract: A memory stack structure including a memory film and a vertical semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulating layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulating layers, a backside blocking dielectric layer may be formed in the backside recesses and sidewalls of the memory stack structures. A metallic barrier material portion can be formed in each backside recess. A metallic material portion is formed on the metallic barrier material portion. Subsequently, a metal portion comprising a material selected from cobalt and ruthenium is formed directly on a sidewall of the metallic barrier material portion and a sidewall of the metallic material portion and an overlying insulating surface and an underlying insulating surface.Type: GrantFiled: June 15, 2017Date of Patent: August 11, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Rahul Sharangpani, Raghuveer Makala, Yanli Zhang, Yao-Sheng Lee
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Patent number: 10497711Abstract: A three-dimensional non-volatile memory is provided with reduced programming variation across word lines. The gate lengths of word lines decrease from the top to the bottom of the memory hole. Increased programming speeds due to a narrow memory hole are offset by a smaller gate length at corresponding positions. A blocking dielectric thickness may also be varied, independently or in combination with a variable word line thickness. The blocking dielectric is formed with a horizontal thickness that is larger at regions adjacent to the lower word line layers and smaller at regions adjacent to the upper word line layers. The larger thickness at the lower word line layers reduces the programming speed in the memory hole for the lower word lines relative to the upper word lines. A variance in programming speed resulting from differences in memory hole diameter may be offset by a corresponding variance in blocking dielectric thickness.Type: GrantFiled: December 19, 2017Date of Patent: December 3, 2019Assignee: SanDisk Technologies LLCInventors: Ashish Baraskar, Liang Pang, Yanli Zhang, Raghuveer Makala, Yingda Dong
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Publication number: 20180122814Abstract: A three-dimensional non-volatile memory is provided with reduced programming variation across word lines. The gate lengths of word lines decrease from the top to the bottom of the memory hole. Increased programming speeds due to a narrow memory hole are offset by a smaller gate length at corresponding positions. A blocking dielectric thickness may also be varied, independently or in combination with a variable word line thickness. The blocking dielectric is formed with a horizontal thickness that is larger at regions adjacent to the lower word line layers and smaller at regions adjacent to the upper word line layers. The larger thickness at the lower word line layers reduces the programming speed in the memory hole for the lower word lines relative to the upper word lines. A variance in programming speed resulting from differences in memory hole diameter may be offset by a corresponding variance in blocking dielectric thickness.Type: ApplicationFiled: December 19, 2017Publication date: May 3, 2018Applicant: SanDisk Technologies LLCInventors: Ashish Baraskar, Liang Pang, Yanli Zhang, Raghuveer Makala, Yingda Dong
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Patent number: 9960180Abstract: Memory openings can be formed through an alternating stack of insulating layers and sacrificial material layers. Memory stack structures including charge storage elements can be formed in the memory openings. Inter-level charge leakage in a three-dimensional memory device including a charge trapping layer can be minimized by employing a thin continuous charge trapping material layer within each memory opening. After removal of the sacrificial material layers and formation of backside recesses, discrete charge trapping material portions can be formed by selective growth of a charge trapping material from physically exposed surfaces of each thin continuous charge trapping material layer. The discrete charge trapping material portions can function as primary charge storage regions, and inter-level charge leakage can be minimized by the small thickness of the thin continuous charge trapping material layer.Type: GrantFiled: March 27, 2017Date of Patent: May 1, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Fei Zhou, Raghuveer Makala, Rahul Sharangpani, Keerti Shukla, Yanli Zhang, Peng Zhang
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Publication number: 20180033794Abstract: A three-dimensional non-volatile memory is provided with reduced programming variation across word lines. The gate lengths of word lines decrease from the top to the bottom of the memory hole. Increased programming speeds due to a narrow memory hole are offset by a smaller gate length at corresponding positions. A blocking dielectric thickness may also be varied, independently or in combination with a variable word line thickness. The blocking dielectric is formed with a horizontal thickness that is larger at regions adjacent to the lower word line layers and smaller at regions adjacent to the upper word line layers. The larger thickness at the lower word line layers reduces the programming speed in the memory hole for the lower word lines relative to the upper word lines. A variance in programming speed resulting from differences in memory hole diameter may be offset by a corresponding variance in blocking dielectric thickness.Type: ApplicationFiled: July 27, 2016Publication date: February 1, 2018Applicant: SanDisk Technologies LLCInventors: Ashish Baraskar, Liang Pang, Yanli Zhang, Raghuveer Makala, Yingda Dong
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Publication number: 20170352669Abstract: A memory stack structure including a memory film and a vertical semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulating layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulating layers, a backside blocking dielectric layer may be formed in the backside recesses and sidewalls of the memory stack structures. A metallic barrier material portion can be formed in each backside recess. A metallic material portion is formed on the metallic barrier material portion. Subsequently, a metal portion comprising a material selected from cobalt and ruthenium is formed directly on a sidewall of the metallic barrier material portion and a sidewall of the metallic material portion and an overlying insulating surface and an underlying insulating surface.Type: ApplicationFiled: June 15, 2017Publication date: December 7, 2017Inventors: Rahul Sharangpani, Raghuveer Makala, Yanli Zhang, Yao-Sheng Lee
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Patent number: 8435831Abstract: Non-volatile storage elements having a reversible resistivity-switching element and techniques for fabricating the same are disclosed herein. The reversible resistivity-switching element may be formed by depositing an oxygen diffusion resistant material (e.g., heavily doped Si, W, WN) over the top electrode. A trap passivation material (e.g., fluorine, nitrogen, hydrogen, deuterium) may be incorporated into one or more of the bottom electrode, a metal oxide region, or the top electrode of the reversible resistivity-switching element. One embodiment includes a reversible resistivity-switching element having a bi-layer capping layer between the metal oxide and the top electrode. Fabricating the device may include depositing (un-reacted) titanium and depositing titanium oxide in situ without air break. One embodiment includes incorporating titanium into the metal oxide of the reversible resistivity-switching element.Type: GrantFiled: November 9, 2010Date of Patent: May 7, 2013Assignee: SanDisk 3D LLCInventors: Deepak C. Sekar, Franz Kreupl, Raghuveer Makala, Peter Rabkin
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Patent number: 8329512Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.Type: GrantFiled: May 3, 2012Date of Patent: December 11, 2012Assignee: SanDisk 3D LLCInventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen, Raghuveer Makala, Vance Dunton
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Publication number: 20120276744Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.Type: ApplicationFiled: May 3, 2012Publication date: November 1, 2012Applicant: SanDisk 3D LLCInventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen, Raghuveer Makala, Vance Dunton
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Patent number: 8263420Abstract: Optimized electrodes for ReRAM memory cells and methods for forming the same are discloses. One aspect comprises forming a first electrode, forming a state change element in contact with the first electrode, treating the state change element, and forming a second electrode. Treating the state change element increases the barrier height at the interface between the second electrode and the state change element. Another aspect comprises forming a first electrode in a manner to deliberately establish a certain degree of amorphization in the first electrode, forming a state change element in contact with the first electrode. The degree of amorphization of the first electrode is either at least as great as the degree of amorphization of the state change element or no more than 5 percent less than the degree of amorphization of the state change element.Type: GrantFiled: February 3, 2009Date of Patent: September 11, 2012Assignee: SanDisk 3D LLCInventors: Depak C. Sekar, April Schricker, Xiying Chen, Klaus Schuegraf, Raghuveer Makala
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Patent number: 8241969Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.Type: GrantFiled: August 24, 2011Date of Patent: August 14, 2012Assignee: SanDisk 3D LLCInventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen, Raghuveer Makala, Vance Dunton
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Publication number: 20110306174Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.Type: ApplicationFiled: August 24, 2011Publication date: December 15, 2011Inventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen, Raghuveer Makala, Vance Dunton
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Patent number: 8026178Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.Type: GrantFiled: January 12, 2010Date of Patent: September 27, 2011Assignee: SanDisk 3D LLCInventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen, Raghuveer Makala, Vance Dunton
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Publication number: 20110227026Abstract: Non-volatile storage elements having a reversible resistivity-switching element and techniques for fabricating the same are disclosed herein. The reversible resistivity-switching element may be formed by depositing an oxygen diffusion resistant material (e.g., heavily doped Si, W, WN) over the top electrode. A trap passivation material (e.g., fluorine, nitrogen, hydrogen, deuterium) may be incorporated into one or more of the bottom electrode, a metal oxide region, or the top electrode of the reversible resistivity-switching element. One embodiment includes a reversible resistivity-switching element having a bi-layer capping layer between the metal oxide and the top electrode. Fabricating the device may include depositing (un-reacted) titanium and depositing titanium oxide in situ without air brake. One embodiment includes incorporating titanium into the metal oxide of the reversible resistivity-switching element.Type: ApplicationFiled: November 9, 2010Publication date: September 22, 2011Inventors: Deepak C. Sekar, Franz Kreupl, Raghuveer Makala, Peter Rabkin, Chu-Chen Fu, Tong Zhang
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Publication number: 20110171815Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.Type: ApplicationFiled: January 12, 2010Publication date: July 14, 2011Inventors: Natalie NGUYEN, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen, Raghuveer Makala, Vance Dunton
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Publication number: 20080093211Abstract: A method of functionalizing a carbon nanotube includes providing a carbon nanotube, irradiating at least one exposed portion of the nanotube surface with ions to generate defect sites on the at least one exposed portion, and forming at least one functional group at a defect site. The method optionally includes attaching a nanostructure to the at least one functional group.Type: ApplicationFiled: December 26, 2006Publication date: April 24, 2008Inventors: Ganapathiraman Ramanath, Raghuveer Makala
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Publication number: 20080089829Abstract: Controllably aligned carbon nanotubes are grown, without the use of a predeposition catalyst, on electrically conducting templates that form an electrical contact with the nanotubes. The method allows fabrication of nanotube-based devices with built-in back-side electrical contacts on silicon and other substrate surfaces.Type: ApplicationFiled: October 13, 2006Publication date: April 17, 2008Inventors: Ramanath Ganapathiraman, Saurabh Agrawal, Matthew J. Frederick, Raghuveer Makala