Patents by Inventor Raghuveer S. Makala

Raghuveer S. Makala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200395380
    Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate including a single crystalline substrate semiconductor material, and memory stack structures extending through the alternating stack and containing a respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die contains a peripheral circuitry.
    Type: Application
    Filed: August 27, 2020
    Publication date: December 17, 2020
    Inventors: Adarsh Rajashekhar, Raghuveer S. Makala, Fei Zhou, Rahul Sharangpani
  • Publication number: 20200395310
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers and the memory stack structures. Electrically conductive layers are formed in the backside recesses. Each of the electrically conductive layers includes a molybdenum-containing conductive liner and a metal fill portion including a metal other than molybdenum.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 17, 2020
    Inventors: Yusuke MUKAE, Naoki TAKEGUCHI, Kensuke YAMAGUCHI, Raghuveer S. MAKALA, Yujin TERASAWA
  • Patent number: 10868025
    Abstract: In-process source-level material layers including a source-level sacrificial layer are formed over a substrate. An alternating stack of insulating layers and sacrificial material layers is formed over the in-process source-level material layers. A memory opening is formed through the alternating stack, and is filled with a memory film and a sacrificial opening fill structure. The source-level sacrificial layer is replaced with a source contact layer including a doped polycrystalline semiconductor material. The source contact layer can be formed by diffusing a metal in a metallic catalyst material through a semiconductor fill material layer that fills a source cavity formed by removal of the source-level sacrificial layer. The sacrificial opening fill structure is replaced with a vertical semiconductor channel, which can be formed with large grains due to large crystal sizes in the source contact layer. The sacrificial material layers are replaced with electrically conductive layers.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: December 15, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fei Zhou, Adarsh Rajashekhar, Rahul Sharangpani, Raghuveer S. Makala
  • Publication number: 20200388626
    Abstract: A memory device includes a silicon-germanium source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the silicon-germanium source contact layer, and a memory stack structure vertically extending through the alternating stack. The memory stack structure comprises a memory film and a vertical semiconductor channel that contacts the memory film. The silicon-germanium source contact layer contacts a cylindrical portion of an outer sidewall of the vertical semiconductor channel. Logic circuits for operating the memory elements may be provided on a substrate within a same semiconductor die, or may be provided in another semiconductor die that is bonded to the semiconductor die containing the memory device.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Inventors: Ashish BARASKAR, Raghuveer S. MAKALA, Peter RABKIN
  • Publication number: 20200388688
    Abstract: A memory device includes a silicon-germanium source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the silicon-germanium source contact layer, and a memory stack structure vertically extending through the alternating stack. The memory stack structure comprises a memory film and a vertical semiconductor channel that contacts the memory film. The silicon-germanium source contact layer contacts a cylindrical portion of an outer sidewall of the vertical semiconductor channel. Logic circuits for operating the memory elements may be provided on a substrate within a same semiconductor die, or may be provided in another semiconductor die that is bonded to the semiconductor die containing the memory device.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Inventors: Ashish BARASKAR, Raghuveer S. MAKALA, Peter RABKIN
  • Patent number: 10847408
    Abstract: A first semiconductor die and a second semiconductor die can be bonded in a manner that enhances alignment of bonding pads. Non-uniform deformation of a first wafer including first semiconductor dies can be compensated for by forming a patterned stress-generating film on a backside of the first wafer. Metallic bump portions can be formed on concave surfaces of metallic bonding pads by a selective metal deposition process to reduce gaps between pairs of bonded metallic bonding pads. Pad-to-pad pitch can be adjusted on a semiconductor die to match the pad-to-pad pitch of another semiconductor die employing a tilt-shift operation in a lithographic exposure tool. A chuck configured to provide non-uniform displacement across a wafer can be employed to hold a wafer in a contoured shape for bonding with another wafer in a matching contoured position. Independently height-controlled pins can be employed to hold a wafer in a non-planar configuration.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: November 24, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Senaka Kanakamedala, Yao-Sheng Lee, Jian Chen
  • Patent number: 10840259
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing molybdenum portions located over a substrate, memory stack structures extending through the alternating stack, and including a memory film and a vertical semiconductor channel, and a backside blocking dielectric layer of a dielectric oxide material including aluminum atoms and at least one of lanthanum or zirconium atoms which directly contacts the molybdenum portions.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: November 17, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Peter Rabkin, Raghuveer S. Makala, Masaaki Higashitani
  • Patent number: 10818542
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Drain-select-level trenches through an upper subset of the sacrificial material layers, and backside trenches are formed through each layer of the alternating stack. Backside recesses are formed by removing the sacrificial material layers. A first electrically conductive material and a second electrically conductive material are sequentially deposited in the backside recesses and the drain-select-level trenches. Portions of the second electrically conductive material and the first electrically conductive material may be removed by at least one anisotropic etch process from the drain-select-level trenches to provide drain-select-level electrically conductive layers as multiple groups that are laterally spaced apart and electrically isolated from one another by cavities within the drain-select-level trenches.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: October 27, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Fei Zhou, Raghuveer S. Makala
  • Publication number: 20200335487
    Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry.
    Type: Application
    Filed: June 30, 2020
    Publication date: October 22, 2020
    Inventors: Adarsh RAJASHEKHAR, Raghuveer S. MAKALA, Fei ZHOU
  • Publication number: 20200335516
    Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry.
    Type: Application
    Filed: June 30, 2020
    Publication date: October 22, 2020
    Inventors: Adarsh RAJASHEKHAR, Raghuveer S. MAKALA, Fei ZHOU
  • Patent number: 10811431
    Abstract: A memory device includes a semiconductor channel extending between a source region and a drain region, a plurality of pass gate electrodes, a plurality of word lines, a gate dielectric located between the semiconductor channel and the plurality of pass gate electrodes, and ferroelectric material portions located between the semiconductor channel and the plurality of word lines.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 20, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Yanli Zhang
  • Patent number: 10804282
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate, and memory stack structures are formed through the alternating stack. A backside trench is formed through the alternating stack, and backside recesses are formed by removing the sacrificial material layers. An undoped aluminum oxide backside blocking dielectric layer is formed in the backside recesses and on sidewalls the backside trench. A portion of the undoped aluminum oxide backside blocking dielectric layer located at an upper end of the backside trench is converted into a carbon-doped aluminum oxide layer. An electrically conductive material is deposited in the backside recesses and at peripheral regions of the backside trench. The electrically conductive material at the peripheral regions of the backside trench is removed by an etch process, with the carbon-doped aluminum oxide layer providing etch resistivity during the etch process.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: October 13, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ashish Baraskar, Fei Zhou, Ching-Huang Lu, Raghuveer S. Makala
  • Patent number: 10804291
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a single crystalline semiconductor layer, a single crystal epitaxial source semiconductor layer located between the single crystalline semiconductor layer and the alternating stack and epitaxially aligned to the single crystalline semiconductor layer, and a memory stack structure vertically extending through the alternating stack and containing a memory film and an epitaxial vertical semiconductor channel including a single crystal semiconductor material that is epitaxially aligned to the epitaxial source semiconductor layer at an interface.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: October 13, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Adarsh Rajashekhar, Fei Zhou, Rahul Sharangpani, Raghuveer S. Makala
  • Patent number: 10797061
    Abstract: Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 6, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Akio Nishida, Toshihiro Iizuka, Rahul Sharangpani, Raghuveer S. Makala, Adarsh Rajashekhar, Fei Zhou, Srikanth Ranganathan
  • Patent number: 10797060
    Abstract: Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 6, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Adarsh Rajashekhar, Fei Zhou, Srikanth Ranganathan, Akio Nishida, Toshihiro Iizuka
  • Publication number: 20200312706
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Drain-select-level trenches through an upper subset of the sacrificial material layers, and backside trenches are formed through each layer of the alternating stack. Backside recesses are formed by removing the sacrificial material layers. A first electrically conductive material and a second electrically conductive material are sequentially deposited in the backside recesses and the drain-select-level trenches. Portions of the second electrically conductive material and the first electrically conductive material may be removed by at least one anisotropic etch process from the drain-select-level trenches to provide drain-select-level electrically conductive layers as multiple groups that are laterally spaced apart and electrically isolated from one another by cavities within the drain-select-level trenches.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 1, 2020
    Inventors: Zhixin Cui, Fei Zhou, Raghuveer S. Makala
  • Publication number: 20200312875
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Drain-select-level trenches through an upper subset of the sacrificial material layers, and backside trenches are formed through each layer of the alternating stack. Backside recesses are formed by removing the sacrificial material layers. A first electrically conductive material and a second electrically conductive material are sequentially deposited in the backside recesses and the drain-select-level trenches. Portions of the second electrically conductive material and the first electrically conductive material may be removed by at least one anisotropic etch process from the drain-select-level trenches to provide drain-select-level electrically conductive layers as multiple groups that are laterally spaced apart and electrically isolated from one another by cavities within the drain-select-level trenches.
    Type: Application
    Filed: May 29, 2020
    Publication date: October 1, 2020
    Inventors: Zhixin Cui, Fei Zhou, Raghuveer S. Makala
  • Patent number: 10790300
    Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate including a single crystalline substrate semiconductor material, and memory stack structures extending through the alternating stack and containing a respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die contains a peripheral circuitry.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: September 29, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Adarsh Rajashekhar, Raghuveer S. Makala, Fei Zhou, Rahul Sharangpani
  • Publication number: 20200295039
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing molybdenum portions located over a substrate, memory stack structures extending through the alternating stack, and including a memory film and a vertical semiconductor channel, and a backside blocking dielectric layer of a dielectric oxide material including aluminum atoms and at least one of lanthanum or zirconium atoms which directly contacts the molybdenum portions.
    Type: Application
    Filed: May 28, 2020
    Publication date: September 17, 2020
    Inventors: Peter RABKIN, Raghuveer S. MAKALA, Masaaki HIGASHITANI
  • Publication number: 20200286907
    Abstract: A combination of an alternating stack and a memory opening fill structure is provided over a substrate. The alternating stack includes insulating layers and electrically conductive layers. The memory opening fill structure vertically extends through the alternating stack, and includes a memory film, a vertical semiconductor channel, and a core structure comprising a core material. A phase change material is employed for the core material. A volume expansion is induced in in the core material by performing an anneal process that induces a microstructural change within the core material. The volume expansion in the core material induces a lateral compressive strain and a vertical tensile strain within the vertical semiconductor channel. The vertical tensile strain enhances charge mobility in the vertical semiconductor channel, and increases the on-current of the vertical semiconductor channel.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventors: Chun GE, Yanli ZHANG, Fei ZHOU, Raghuveer S. MAKALA