Patents by Inventor Raghuveer S. Makala

Raghuveer S. Makala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220139949
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Each electrically conductive layer within a subset of the electrically conductive layers includes a respective first metal layer containing an elemental metal and a respective first metal silicide layer containing a metal silicide of the elemental metal. Memory openings vertically extend through the alternating stack. Memory opening fill structures located within the memory openings can include a respective memory film and a respective vertical semiconductor channel.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Inventors: Rahul SHARANGPANI, Raghuveer S. MAKALA, Fei ZHOU, Adarsh RAJASHEKHAR
  • Publication number: 20220139960
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of charge storage elements, a vertical semiconductor channel, a ferroelectric material layer located between the vertical stack of charge storage elements and the vertical semiconductor channel, and a blocking dielectric layer located between the ferroelectric material layer and the vertical semiconductor channel. A tunneling dielectric layer is located between at least one of the electrically conductive layers and the vertical stack of charge storage elements.
    Type: Application
    Filed: January 19, 2022
    Publication date: May 5, 2022
    Inventors: Ramy Nashed Bassely SAID, Adarsh RAJASHEKHAR, Senaka KANAKAMEDALA, Raghuveer S. MAKALA
  • Patent number: 11322509
    Abstract: A memory device includes a silicon-germanium source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the silicon-germanium source contact layer, and a memory stack structure vertically extending through the alternating stack. The memory stack structure comprises a memory film and a vertical semiconductor channel that contacts the memory film. The silicon-germanium source contact layer contacts a cylindrical portion of an outer sidewall of the vertical semiconductor channel. Logic circuits for operating the memory elements may be provided on a substrate within a same semiconductor die, or may be provided in another semiconductor die that is bonded to the semiconductor die containing the memory device.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: May 3, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ashish Baraskar, Raghuveer S. Makala, Peter Rabkin
  • Publication number: 20220130853
    Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film, a vertical semiconductor channel, a source region containing a metal silicide material contacting a first end of the vertical semiconductor channel, and a drain region containing a doped semiconductor material contacting a second end of the vertical semiconductor channel, and a source contact layer contacting the source region.
    Type: Application
    Filed: October 28, 2020
    Publication date: April 28, 2022
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Fei Zhou, Adarsh Rajashekhar
  • Patent number: 11309301
    Abstract: Multiple bonded units are provided, each of which includes a respective front-side die and a backside die. The two dies in each bonded unit may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The multiple bonded units can be attached such that front-side external bonding pads have physically exposed surfaces that face upward and backside external bonding pads of each bonded unit have physically exposed surfaces that face downward. A first set of bonding wires can connect a respective pair of front-side external bonding pads, and a second set of bonding wires can connect a respective pair of backside external bonding pads.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: April 19, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fei Zhou, Raghuveer S. Makala, Rahul Sharangpani, Adarsh Rajashekhar
  • Patent number: 11309332
    Abstract: A three-dimensional ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where each of the electrically conductive layers contains a transition metal element-containing conductive liner and a conductive fill material portion, a vertical semiconductor channel extending vertically through the alternating stack, a vertical stack of tubular transition metal element-containing conductive spacers laterally surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers, and a ferroelectric material layer located between the vertical stack of tubular transition metal element-containing conductive spacers and the transition metal element-containing conductive liner.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: April 19, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Adarsh Rajashekhar, Raghuveer S. Makala, Rahul Sharangpani, Seung-Yeul Yang, Fei Zhou
  • Patent number: 11302716
    Abstract: A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers, and a combination of a ferroelectric dielectric layer and an electrically conductive layer within each of the backside recesses. The electrically conductive layer is laterally spaced from a respective one of the discrete intermediate metallic electrodes by the ferroelectric dielectric layer. Ferroelectric-metal-insulator memory elements are formed around the vertical semiconductor channel.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: April 12, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Yanli Zhang, Fei Zhou, Rahul Sharangpani, Adarsh Rajashekhar, Seung-Yeul Yang
  • Patent number: 11302713
    Abstract: A stack including a silicon oxide layer, a germanium-containing layer, and a III-V compound semiconductor layer is formed over a substrate. An alternating stack of insulating layers and spacer material layers is formed over the III-V compound semiconductor layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and into the III-V compound semiconductor layer. Memory opening fill structures including a memory film and a vertical semiconductor channel are formed in the memory openings. The vertical semiconductor channels can include a III-V compound semiconductor channel material that is electrically connected to the III-V compound semiconductor layer. The substrate and at least a portion of the silicon oxide layer can be subsequently detached.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: April 12, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ashish Kumar Baraskar, Raghuveer S. Makala, Peter Rabkin
  • Patent number: 11296101
    Abstract: A three-dimensional memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers located over a substrate, an etch stop material layer located over the first-tier alternating stack, a second-tier alternating stack of second insulating layers and second electrically conductive layers located over the etch stop material layer, inter-tier memory openings vertically extending through the second-tier alternating stack, the etch stop material layer, and the first-tier alternating stack, and memory opening fill structures each including a memory film and a vertical semiconductor channel located in the inter-tier memory openings. The material of the etch stop material layer is different from materials of the first insulating layers, the second insulating layers, the first electrically conductive layers, and the second electrically conductive layers.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: April 5, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yao-Sheng Lee, Senaka Kanakamedala, Raghuveer S. Makala, Johann Alsmeier
  • Patent number: 11296028
    Abstract: A structure, such as a semiconductor device, includes metal line structures located over a substrate and laterally spaced apart from each other. Each of the metal line structures includes planar metallic liner including a first metal element and a metal line body portion includes a second metal element that is different from the first metal element. Metal-organic framework (MOF) material portions are located between neighboring pairs of the metal line structures and contain metal ions or clusters of the first metal element and organic ligands connected to the metal ions or clusters of the first metal element. Air gaps may be formed in the MOF material portions to further reduce the effective dielectric constant.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: April 5, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ramy Nashed Bassely Said, Senaka Kanakamedala, Fei Zhou, Raghuveer S. Makala, Yao-Sheng Lee
  • Publication number: 20220093644
    Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel and a memory film. The memory film includes a contoured blocking dielectric layer including sac-shaped lateral protrusions located at levels of the electrically conductive layers, a tunneling dielectric layer in contact with the vertical semiconductor channel, and a vertical stack of charge storage material portions located within volumes enclosed by the sac-shaped lateral protrusions.
    Type: Application
    Filed: December 7, 2021
    Publication date: March 24, 2022
    Inventors: Rahul SHARANGPANI, Raghuveer S. MAKALA, Kartik SONDHI, Ramy Nashed Bassely SAID, Senaka KANAKAMEDALA
  • Patent number: 11282857
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and a memory stack structure vertically extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel and a memory film. The vertical semiconductor channel can include a III-V compound semiconductor channel material. A III-V compound substrate semiconductor layer or a III-V compound semiconductor source region can be used to provide low-resistance electrical connection to a bottom end of the vertical semiconductor channel, and a drain region including a graded III-V compound semiconductor material can be used to provide low-resistance electrical connection to a top end of the vertical semiconductor channel.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: March 22, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ashish Baraskar, Peter Rabkin, Raghuveer S. Makala
  • Patent number: 11282848
    Abstract: A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers, and a combination of a ferroelectric dielectric layer and an electrically conductive layer within each of the backside recesses. The electrically conductive layer is laterally spaced from a respective one of the discrete intermediate metallic electrodes by the ferroelectric dielectric layer. Ferroelectric-metal-insulator memory elements are formed around the vertical semiconductor channel.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: March 22, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Yanli Zhang, Fei Zhou, Rahul Sharangpani, Adarsh Rajashekhar, Seung-Yeul Yang
  • Publication number: 20220059462
    Abstract: A semiconductor structure includes first metal lines located above at least one semiconductor device, and a continuous metal organic framework (MOF) material layer including lower MOF portions that are located between neighboring pairs of first metal lines and an upper MOF matrix portion that continuously extends over the first metal lines and connected to each of the lower MOF portions.
    Type: Application
    Filed: August 24, 2020
    Publication date: February 24, 2022
    Inventors: Ramy Nashed Bassely SAID, Raghuveer S. MAKALA, Senaka KANAKAMEDALA, Yao-Sheng LEE
  • Publication number: 20220045087
    Abstract: A memory device can include a strained single-crystalline silicon layer and an alternating stack of insulating layers and electrically conductive layers located over the strained single-crystalline silicon layer. A memory opening fill structure extending through the alternating stack may include an epitaxial silicon-containing pedestal channel portion, and a vertical semiconductor channel, and a vertical stack of memory elements located adjacent to the vertical semiconductor channel. Additionally or alternatively, a drain region can include a semiconductor drain portion and a nickel-aluminum-semiconductor alloy drain portion.
    Type: Application
    Filed: August 4, 2020
    Publication date: February 10, 2022
    Inventors: Ashish BARASKAR, Raghuveer S. MAKALA, Peter RABKIN
  • Publication number: 20220042171
    Abstract: A method of depositing tungsten over a substrate includes disposing the substrate into a vacuum enclosure of a tungsten deposition apparatus, performing a first tungsten deposition process that deposits a first tungsten layer over a physically exposed surface of the substrate by flowing a fluorine-containing tungsten precursor gas into the vacuum enclosure, performing an in-situ oxidation process by exposing the first tungsten layer to an oxidation agent gas while the substrate remains within the vacuum enclosure without breaking vacuum and forming a tungsten oxyfluoride gas which is pumped out of the vacuum enclosure, and performing a second tungsten deposition process that deposits a second tungsten layer on the first tungsten layer by flowing the fluorine-containing tungsten precursor gas into the vacuum enclosure in a second tungsten deposition process after the in-situ oxidation process.
    Type: Application
    Filed: August 7, 2020
    Publication date: February 10, 2022
    Inventors: Fei ZHOU, Raghuveer S. MAKALA, Rahul SHARANGPANI, Yusuke MUKAE, Naoki TAKEGUCHI
  • Publication number: 20220045088
    Abstract: A memory device can include a strained single-crystalline silicon layer and an alternating stack of insulating layers and electrically conductive layers located over the strained single-crystalline silicon layer. A memory opening fill structure extending through the alternating stack may include an epitaxial silicon-containing pedestal channel portion, and a vertical semiconductor channel, and a vertical stack of memory elements located adjacent to the vertical semiconductor channel Additionally or alternatively, a drain region can include a semiconductor drain portion and a nickel-aluminum-semiconductor alloy drain portion.
    Type: Application
    Filed: August 4, 2020
    Publication date: February 10, 2022
    Inventors: Ashish BARASKAR, Raghuveer S. MAKALA, Peter RABKIN
  • Patent number: 11244958
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Drain-select-level trenches through an upper subset of the sacrificial material layers, and backside trenches are formed through each layer of the alternating stack. Backside recesses are formed by removing the sacrificial material layers. A first electrically conductive material and a second electrically conductive material are sequentially deposited in the backside recesses and the drain-select-level trenches. Portions of the second electrically conductive material and the first electrically conductive material may be removed by at least one anisotropic etch process from the drain-select-level trenches to provide drain-select-level electrically conductive layers as multiple groups that are laterally spaced apart and electrically isolated from one another by cavities within the drain-select-level trenches.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: February 8, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Fei Zhou, Raghuveer S. Makala
  • Patent number: 11244953
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and word lines that are made of molybdenum layers located over a substrate, and memory stack structures extending through each layer in the alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Each memory film includes a vertical stack of discrete tubular dielectric metal oxide spacers in contact with a respective one of the molybdenum layers, a continuous silicon oxide blocking dielectric layer contacting an inner sidewall of each of the tubular dielectric metal oxide spacers, a vertical stack of charge storage material portions, and a tunneling dielectric layer contacting each of the charge storage material portions and the vertical semiconductor channel.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: February 8, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Senaka Kanakamedala, Raghuveer S. Makala, Yao-Sheng Lee
  • Patent number: 11239254
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel, a vertical stack of majority germanium layers each containing at least 51 atomic percent germanium, and a vertical stack of ferroelectric dielectric layers.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: February 1, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Adarsh Rajashekhar, Raghuveer S. Makala, Fei Zhou, Seung-Yeul Yang